Bit-line drive circuit for a semiconductor memory

A semiconductor memory comprising:

• a plurality of word lines and a plurality of bit line pairs;
• memory cells which are coupled to the word lines and the bit line pairs, wherein each memory cell is arranged between respective crosspoints of a word line and a bit line pair and includes a flip-flop comprised of field effect transistors;
• first bipolar transistors having bases which are coupled to respective bit lines of the bit line pairs, wherein each said first bipolar transistor outputs information of the memory cell, coupled to the same bit line of the bit line pair to which it is coupled, from its collector in accordance with first and second signals which are inputted to their bases and emitters;
• second bipolar transistors having emitters which are coupled to respective bit lines of the bit line pairs, wherein each said second bipolar transistor supplies a charge current to the bit line of the bit line pair to which it is coupled in accordance with third signals which are inputted to their bases;
• and
• third bipolar transistors having collectors which are coupled to respective bit lines of the bit line pairs, wherein each said third bipolar transistor supplies a discharge current to the bit line of said respective bit lines to which it is coupled in accordance with fourth and fifth signals which are inputted to their bases and their emitters,
• wherein said third signals have higher (lower) potential levels than said fourth signals, and wherein each third bipolar transistor is a bipolar transistor which supplies a current to the bit line of the respective bit lines to which its collector is coupled only when data is being written into a memory cell coupled between the bit line pair to which the third bipolar transistors are coupled.