Integrated-circuit chip and system for developing timing reference signals for use in high-resolution CRT display equipment

In a control system for high-resolution CRT graphics display equipment of the type including a graphics processor and a frame buffer including video storage banks and port means from which digital pixel signals are serially clocked;

• a single MOS integrated-circuit (IC) chip providing:
• pixel receiving means to temporarily store digital signals developed by said port means of said frame buffer and including a clock input terminal;
• clock generator means having first and second output means providing two output clock signals at different frequencies;
• means coupling said first output means to said clock input terminal of said pixel receiving means to clock-in the pixel signals directed thereto;
• a serial clock generator coupled to said second output means of said clock generator means and responsive to the clock signals of said second output means to produce corresponding serial clock signals for said port means to clock-out digital pixel signals therefrom;
• said control system further including:
• an external signal processing device coupled between said port means and said pixel receiving means and operable to receive said clocked-out digital pixel signals from said port means and to direct corresponding pixel signals to said pixel receiving means;
• a synchronizing signal terminal at said external signal processing device to receive clock signals for synchronizing the development of pixel signals from said external processing device;
• and
• means for coupling said first output means of said clock generator means to said synchronizing signal terminal of said external signal processing device to provide clock signals thereto to effect synchronism between the pixel signals from said external signal processing device and the clocking of said pixel receiving means.

For use in a control system for high-resolution CRT graphics display equipment of the type including a frame buffer and a graphics processor, wherein said frame buffer includes digital signal storage means and port means from which multi-bit digital data signals are serially clocked;

• a single MOS integrated-circuit (IC) chip formed with a plurality of transistors and having connection pins to establish interconnection with said frame buffer and said graphics processor;
• said chip serving as the master timing control for the video signals of said system and incorporating:
• (a) pixel receiving means to temporarily store digital data signals received from said port means of said frame buffer;
• (b) a first pin to receive clock signals from an external high-frequency clock signal source;
• (c) a clock generator within said chip having an input connected to said first pin to receive the external clock signals and having output means for producing corresponding clock signals to serve as video timing signals;
• (d) a second pin coupled to said output means of said clock generator to provide a load-out signal;
• and
• (e) a third pin arranged to be alternatively connected to said second pin (1) directly, and (2) indirectly through an external device;
• said third pin being connected to said pixel receiving means to provide a load-in signal serving to load digital data signals from said port means of said frame buffer into said pixel receiving means.

A single MOS integrated circuit (IC) for generating the analog control signals for a cathode ray tube (CRT) display, said IC including:

• (a) a plurality of groups of input pins for receiving digital input signals representing the intensities of pixels to be displayed on the CRT;
• (b) clock generator means receiving a pixel clock signal and producing a first output clock signal of frequency lower than the frequency of said pixel clock signal;
• (c) a plurality of storage means respectively coupled to said groups of digital input pins and having output means for each storage means, said storage means including latch means with means receiving a first input clock signal which is lower in frequency than said pixel clock frequency by a ratio "n" where "n" is a positive integer;
• (d) multiplexer means operable to accelerate the outputs of said plurality of storage means into single pixel streams, where the ratio of acceleration is the ratio "n";
• (e) three digital-to-analog converters (DACs) responsive to said pixel streams respectively, said DACs generating said analog control signals for the Red, Green and Blue color guns respectively of the CRT display.

The method of controlling a three-color CRT display by digital signals from a frame buffer to an IC chip including (a) three DACs for developing three analog signals for the CRT, (b) clock signal generator means, and (c) multiplexer means, said method comprising:

• (1) developing from said clock signal generator means a first clock signal for said multiplexer means to provide for accelerating pixel signals sent out from said frame buffer to said chip;
• (2) developing from said clock signal generator means a second clock signal having a frequency different from said first clock signal;
• and
• (3) applying said second clock signal to a pin of said IC to provide for activating an external data processing device which receives pixel signals from said frame buffer and processes the pixel signals prior to application to said IC where the pixel signals can be accelerated by said multiplexer means on said IC chip.