Semiconductor integrated circuit device including high-speed operating circuit and low-speed operating circuit, and system using the same
AssigneesHitachi, Ltd., Hitachi Microcomputer Engineering Ltd.
InventorsTakashi Nara, Yasuhiro Kanzawa, Akira Uragami, Masaou Takahashi
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Abstract
The semiconductor integrated circuit device formed on one semiconductor substrate employs a plurality of first and second circuit blocks constituting functions of the same kind. The first and second circuit blocks, however, are implemented with respectively different types of circuits. The type of circuit employed in the respective first and second circuit blocks is necessarily consistent with the particular operation speed requirements thereof, such as, in connection with high-speed and low-speed circuit requirements for writing into the memory of a display system.
Claims31
A semiconductor integrated circuit device, formed on a semiconductor substrate, to be accessed by at least one of first access means for providing first selecting signals to the semiconductor integrated circuit device and second access means for providing second selecting signals to the semiconductor integrated circuit device, the semiconductor integrated circuit device comprising:
- first external terminals for receiving the first selecting signals;
- second external terminals for receiving the second selecting signals;
- a plurality of memory cells;
- first and second word lines and first and second pairs of data lines coupled to the plurality of memory cells so that each memory cell is coupled to one of the first word lines, one of the second word lines, one pair of the first pairs of data lines, and one pair of the second pairs of data lines;
- first selecting means, coupled between the first external terminals and the first word lines, and for selecting at least one of the plurality of memory cells in accordance with the first selecting signals, wherein the first selecting means operates at a first speed in conformance with the speed requirement for processing of the first selecting signals;
- second selecting means, coupled between the second external terminals and the second word lines, and for selecting at least one of the plurality of memory cells in accordance with the second selecting signals, wherein the second selecting means operates at a second speed which is lower than the first speed and in conformance with the speed requirement for processing of the second selecting signals;
- first sense means, coupled to the first pairs of data lines, and for subsequently amplifying a potential difference appearing between the data lines of a selected one of the first pairs of data lines in response to the selection thereof by the first selecting means;
- and
- second sense means, coupled to the second pairs of data lines, and responsive to an internal read control signal for selectively amplifying a potential difference appearing between the data lines of a selected one of the second pairs of data lines in response to the selection thereof by the second selecting means.
A semiconductor integrated circuit device, formed on a semiconductor substrate, comprising:
- first external terminals for receiving the first selecting signals;
- second external terminals for receiving the second selecting signals;
- a plurality of memory cells;
- first and second word lines and first and second pairs of data lines coupled to the plurality of memory cells so that each memory cell is coupled to one of the first word lines, one of the second word lines, one pair of the first pairs of data lines, and one pair of the second pairs of data lines;
- first selecting means, coupled between the first external terminals and the first word lines, and for selecting at least one of the plurality of memory cells in accordance with the first selecting signals, wherein the first selecting means operates at a first speed in conformance with the speed requirement for processing of the first selecting signals;
- second selecting means, coupled between the second external terminals and the second word lines, and for selecting at least one of the plurality of memory cells in accordance with the second selecting signals, wherein the second selecting means operates at a second speed which is lower than the first speed and in conformance with the speed requirement for processing of the second selecting signals;
- first sense means, coupled to the first pairs of data lines, and for subsequently amplifying a potential difference appearing between the data lines of a selected one of the first pairs of data lines in response to the selection thereof by the first selecting means;
- and
- second sense means, coupled to the second pairs of data lines, and responsive to an internal read control signal for selectively amplifying a potential difference appearing between the data lines of a selected one of the second pairs of data lines in response to the selection thereof by the second selecting means.
Dependencies are inferred from the claim text.