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US 5,397,984 AGranted
Integrated circuit for protecting internal circuitry from high voltage input test signals
AssigneeNEC Corporation
InventorYasuji Koshikawa
Life of this patent
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AssigneeNEC Corporation
InventorYasuji Koshikawa
Estimating the term…
A semiconductor integrated circuit protected against a high voltage testing signal is provided. The integrated circuit includes a first-stage input circuit, a discriminating circuit, a power suppuly circuit and a connecting circuit. The input ends of the-input circuit and the discriminating circuit are connected to one preselected external terminal. The discriminating circuit renders a testing circuit drive signal active to activate when a testing instruction signal higher than an ordinary input signal voltage is applied to the external terminal. When the testing circuit drive signal is active, the power supply circuit disconnects at least one of the positive and negative poles of the power source having polarity opposite to that of the testing instruction signal from the input circuit, and the connecting circuit connects one of the positive and negative poles of the power source having the same polarity as that of the testing instruction signal to the output end of the input circuit.
A semiconductor integrated circuit, comprising:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
Testing of digital circuits: arrangements for setting the Unit Under Test [UUT] in a test mode
Testing of integrated circuits [IC]: using dedicated test connectors, test elements or test circuits on the IC under test
Measuring electric variables
Term ended 28 Jan 2013 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
(1) Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which has a function of entering a test mode when a voltage higher than a power source voltage is applied to an external terminal of the circuit.
(2) Description of the Related Art
FIG. 1 is a circuit diagram showing a semiconductor integrated circuit of the prior art;
FIG. 2 is a circuit diagram showing another semiconductor integrated circuit of the prior art;
FIG. 3 is a block diagram of a semiconductor integrated circuit showing a preferred embodiment of the present invention;
Preferred embodiments of the present invention are described below with reference to the drawings. FIG. 3 is a block diagram showing a semiconductor integrated circuit according to a preferred embodiment of the present invention.
Integrated circuit 100 has a plurality of external terminals (only external terminal 30 is shown in FIG. 3 for simplification), and power is supplied from power source 60 to integrated circuit 100.
An external terminal 30 is selected in advance for application of a super-voltage. The first-stage input circuit 10 receives an input signal applied to the external terminal 30 and outputs an output signal to a succeeding internal circuit.