Duty cycle control circuit
AssigneeSamsung Semiconductor, Inc.
InventorsDaniel Shum, Shufan Chan
Life of this patent
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Abstract
A circuit for converting an input signal with an arbitrary duty cycle to an output signal with a 50 percent duty cycle. A bandpass filter removes unwanted DC and high frequency components from the input signal. A comparator compares the filtered signal to a reference voltage and provides very high gain amplification to produce an output signal having a 50 percent duty cycle. In one embodiment, two bandpass filters are used to condition the signal prior to providing it to the comparator. Each bandpass stage is comprised of a low pass filter followed by a high pass filter.
Claims11
A method of providing a clock signal having a substantially 50% duty cycle comprising the steps of:
- providing an input clock signal having an arbitrary duty cycle to a bandpass filter;
- removing high frequency and DC components from said input clock signal using said bandpass filter to generate a conditioned signal;
- providing said conditioned signal to a comparator and comparing said conditioned signal to a reference;
- generating a clock signal having a first level when said conditioned signal is less than said reference signal and a clock signal having a second level when said conditioned signal is greater than said reference signal.
A method of providing a clock signal having a substantially 50% duty cycle comprising the steps of:
- providing an input clock signal having an arbitrary duty cycle to a first bandpass filter;
- removing high frequency and DC components from said input clock signal using said first bandpass filter to generate a first conditioned signal;
- providing said first conditioned signal to a second bandpass filter;
- removing high frequency and DC components from said first conditioned signal using said second bandpass filter to generate a second conditioned signal;
- providing said second conditioned signal to a comparator and comparing said second conditioned signal to a reference;
- generating a clock signal having a first level when said second conditioned signal is less than said reference signal and a clock signal having a second level when said second conditioned signal is greater than said reference signal.
A circuit for controlling the duty cycle of a signal comprising:
- a bandpass filter for receiving an input signal and for providing a filtered signal, said bandpass filter comprising a plurality of stages, said bandpass filter further comprising amplifying means between said stages;
- a comparator coupled to said bandpass filter for receiving said filtered signal and for providing an output signal;
- and
- a reference voltage coupled to said comparator.
The circuit of claim 9 wherein each of said stages comprises a low pass filter and a high pass filter.
Dependencies are inferred from the claim text.