Buffer system with reduced interference

A buffer circuit system comprising:

• first and second buffer circuits each having an input terminal and an output terminal wherein the output terminal of the first buffer circuit is adapted to be coupled to the input terminal of the second buffer circuit and the input terminal of the first buffer circuit is adapted to receive a signal to be processed by the buffer circuit system, wherein
• the first buffer circuit comprises;
• a first inverter circuit coupled to terminals of a first supply voltage and having an input terminal and an output terminal which comprise said input terminal and said output terminal, respectively, of the first buffer circuit, first means for coupling a second inverter circuit and a first capacitor in series circuit between said input terminal and said output terminal of the first buffer circuit, wherein the second inverter circuit is coupled to terminals of a second supply voltage, means for limiting the voltage swing of an output signal at the output terminal of the first buffer circuit, and means for producing a reference voltage at a further output terminal of the first buffer circuit, and wherein
• the second buffer circuit comprises;
• a third inverter circuit adapted to be coupled to the terminals of the second supply voltage and having an input terminal and an output terminal which comprise said input terminal and said output terminal, respectively, of the second buffer circuit, and a second input terminal adapted to be coupled to the further output terminal of the first buffer circuit so as to receive said reference voltage.

A voltage processing circuit comprising:

• a first inverter circuit having an input terminal for receiving an input voltage and having an output terminal,
• a second inverter circuit,
• a capacitor,
• first means for coupling said second inverter circuit and said second capacitor in series circuit between said input and output terminals,
• second means for coupling the second inverter circuit to first and second terminals of a first D.C. supply voltage,
• third means for coupling the first inverter circuit to first and second terminals of a second D.C. supply voltage that is lower than said first D.C. supply voltage in a manner whereby a voltage swing of an output voltage at the output terminal is limited to a fraction of a voltage swing of an input voltage applied to the input terminal, and
• means coupled to at least one of said D.C. supply voltages for deriving a reference voltage level for said output voltage of the voltage processing circuit.