High-performance insulated-gate field-effect transistor
AssigneeTexas Instruments Incorporated
InventorMehrdad M. Moslehi
Life of this patent
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Abstract
An improved device fabrication method and transistor structure 36 provide shallow, heavily doped, source/drain junction regions 64 and a uniformly doped lower gate region 50 having a high concentration of dopants efficiently distributed near the gate electrode/gate interface 51. The gate, source, and drain terminals of transistor 36 may be interconnected to other neighboring or remote devices through the use of reacted refractory metal interconnect segments 98 and 100. Transistor structure 36 of the present invention may be constructed in an elevated source/drain format to include elevated source/drain junction regions 87 which may be fabricated simultaneous with a primary upper gate electrode region 88. This elevated source/drain junction feature is provided without added device processing complexity.
Claims16
A transistor, comprising:
- an insulating layer adjacent a semiconductor region:
- a first gate conductor region adjacent said insulating layer and opposite said semiconductor region;
- a pair of implanted source/drain regions within said semiconductor region wherein said pair of implanted source/drain regions comprises heavily doped source/drain regions, and further comprising a pair of lightly-doped source/drain regions contacting said heavily doped source/drain regions;
- a second gate conductor region adjacent said first gate conductor region;
- a pair of elevated source/drain regions adjacent and overlying said implanted source/drain regions wherein said elevated source/drain regions comprise a first pair of elevated doped source/drain regions;
- a second pair of elevated source/drain regions overlying said first pair of elevated source/drain regions;
- and
- a reacted refractory metal contact contacting at least one of said second pair of elevated source/drain regions.
A semiconductor device comprising:
- an insulating layer adjacent a semiconductor region and having sidewalls;
- a first gate conductor region having sidewalls adjacent said insulating layer and opposite said semiconductor region;
- sidewall spacers adjacent the sidewalls of said insulating layer, and said gate conductor region;
- source/drain regions formed within said semiconductor region;
- a first pair of elevated source/drain regions adjacent and overlying said source/drain regions;
- a second pair of elevated source/drain regions overlying said first pair of elevated source/drain regions;
- and
- a reacted refractory metal layer contacting at least one of said second pair of elevated source/drain regions.
Dependencies are inferred from the claim text.