Method for fabrication of semiconductor device having polycrystalline silicon and metal silicides
AssigneeAsahi Kasei Microsystems Co., Ltd.
InventorsSachiro Kayanuma, Koji Iki
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Abstract
A method of fabricating a semiconductor device having a semiconductor substrate, a MOS transistor formed on one surface of the semiconductor substrate, and a capacitor is disclosed. The MOS has a gate electrode with a polycrystalline silicon layer and a metal silicide layer. The capacitor includes a first polycrystalline silicon layer which forms a lower electrode layer, an insulating interlayer, and a second polycrystalline silicon layer which forms an upper electrode, the first and second polycrystalline silicon layers sandwiching the insulating interlayer.
Claims9
A method for fabricating a semiconductor device comprising the steps of:
- (a) forming on one surface of a semiconductor substrate a field oxide layer and a gate oxide layer;
- (b) depositing a first polycrystalline silicon layer;
- (c) forming an insulating layer over said first polycrystalline silicon layer;
- (d) depositing a second polycrystalline silicon layer on said insulating layer;
- (e) etching said second polycrystalline silicon layer outside a portion designated as an upper electrode layer of a capacitor;
- (f) selectively covering a first mask over said upper electrode layer and its peripheral portion;
- (g) forming a metal silicide layer;
- (h) forming a second mask over a portion of said metal silicide layer designated as a gate electrode of a MOS transistor;
- and
- (i) etching said first polycrystalline silicon layer and said metal silicide layer to form a gate electrode and a capacitor, said gate electrode comprising a lamination of said first polycrystalline silicon layer and said metal silicide layer, said capacitor comprising a lamination of said first and second polycrystalline silicon layers and said insulating layer.
A method for fabricating a semiconductor device comprising the steps of:
- (a) forming on one surface of a semiconductor substrate a field oxide layer and a gate oxide layer;
- (b) depositing a first polycrystalline silicon layer;
- (c) forming an insulating layer over said first polycrystalline silicon layer;
- (d) depositing a second polycrystalline silicon layer over said insulating layer;
- (e) etching said second polycrystalline silicon layer outside a portion designated as an upper electrode layer of a capacitor;
- (f) selectively covering a first mask over said upper electrode layer and the peripheral surface thereof and a portion designated as a resistor, said resistor comprising a single polycrystalline silicon layer;
- (g) forming a metal silicide layer;
- (h) forming a second mask over a portion of said metal silicide layer designated as a gate electrode of a MOS transistor;
- and
- (i) etching said first polycrystalline silicon layer and said metal silicide layer to form a gate electrode, a capacitor, and a resistor, said gate electrode comprising a lamination of said first polycrystalline silicon layer and said metal silicide layer, said capacitor comprising a lamination of said first and second polycrystalline silicon layers and said insulating interlayer.
Dependencies are inferred from the claim text.