MOS transistor having increased gate-drain capacitance
AssigneeMicrel, Inc.
InventorBernard D. Miller
Life of this patent
Estimating the term…
Abstract
A process is described for providing a self-aligned MOS transistor having a selectable gate-drain capacitance. In a self-aligned process for forming a PMOS transistor, a polysilicon layer is etched to expose portions of an n-type substrate in which it is desired to form p+ drain regions. A deep p.sup.+ drain region is then formed in the surface of the substrate so as to have a large diffusion under the polysilicon layer. This large diffusion results in a high gate-drain capacitance. The polysilicon layer is further etched to form a gate. A self-aligned source is then formed using a separate, relatively shallow p+ diffusion. The selectable gate-drain capacitance obviates the need to form separate capacitors on the substrate to use as gate-drain capacitors.
Claims6
A method for forming a self-aligned MOS transistor, said method comprising the steps of:
- forming a layer of a gate-forming material overlying a surface of a semiconductor substrate of a first conductivity type;
- removing a first portion of said layer to expose a first area of said surface;
- depositing dopants of a second conductivity type in said first area to form a first region self-aligned with said gate-forming material, said first region being of said second conductivity type;
- driving in said dopants in said first region to a selected first gate underdiffusion length to achieve a desired capacitance between said gate-forming material and said first region, wherein said first region serves as a drain region of said MOS transistor;
- removing a second portion of said layer to expose a second area of said surface, a remaining portion of said layer forming a gate for said MOS transistor;
- and
- depositing dopants of said second conductivity type in said second area to form a second region self-aligned with said gate, said second region serving as a source region of said MOS transistor,
- wherein said second region has a second gate underdiffusion length which is substantially less than said first gate underdiffusion length.
Dependencies are inferred from the claim text.