Reconfigurable memory processor

A dynamically reconfigurable memory processor, comprising

• (a) a plurality of memory devices, each having an input and an output;
• (b) a plurality of first processors associated with said memory devices, respectively, each of said processors having an input and an output;
• (c) first selector means connecting the outputs of said memory devices with the inputs of said first processors, whereby an input to each first processor comprises an output from one of said memory devices;
• (d) second selector means connecting the output of each of said first processors with the input of the memory device associated with said first processor, the output of each memory device further being connected with said second selector means, said second selector means comprising a plurality of multiplexers connected with said plurality of memory devices, respectively;
• (e) decoder means for controlling said second selector means to select as an input to said memory devices one of said memory device and first processor outputs;
• and
• (f) a plurality of said memory devices and said first processors are arranged in a group, said group including a single first selector means and a single decoder which are operable to reconfigure said group of memory devices and first processors between a first mode of operation wherein a single memory device is available to any number of said plurality of first processors and a second mode of operation wherein any number of said plurality of memory devices in said group is available to a single processor, whereby the plurality of first processors is effectively reduced to a single processor and the amount of memory available to the single processor is increased by a factor of the number of memory devices.