Method and apparatus for increasing the decoding speed of a microprocessor

A method for increasing a decoding speed of a microprocessor comprising steps of:

• decoding a macroinstruction;
• generating a single initial microinstruction vector from a first generator for simple macroinstructions and for complex macroinstructions having a beginning microinstruction equivalent to a microinstruction vector for a simple macroinstruction;
• simultaneously beginning the generating of any remaining microinstruction vectors for complex macroinstructions from a second generator;
• sequencing microinstruction vectors from the first generator and from the second generator to remaining stages of the microprocessor, wherein the step of sequencing microinstruction vectors from the first generator and from the second generator to remaining stages of the microprocessor comprises steps of:
• generating a signal indicating that the first generator has a microinstruction vector to transfer;
• generating a signal indicating that the second generator has a microinstruction vector to transfer;
• pointing to either the first generator or to the second generator, wherein the step of pointing to either the first generator or to the second generator comprises:
• pointing to the first generator after any microinstruction vector which is a last vector of an instruction;
• pointing to the second generator after any microinstruction vector which is not a last vector of an instruction;
• and
• selecting for transfer a microinstruction vector from the first generator when the first generator has a microinstruction vector to transfer and the first generator is pointed to or from the second generator when the second generator has a microinstruction vector to transfer and the second generator is pointed to.

Apparatus for increasing a decoding speed of a processor, the apparatus comprising:

• a decode circuit coupled to receive a macroinstruction, the decode circuit for generating an initial value indicating a first microinstruction of the macroinstruction, and for generating an entry point value indicating any subsequent microinstruction of the macroinstruction;
• a first microcode generator coupled to receive the initial value, the first microcode generator for generating only a first microinstruction vector for the first microinstruction if the macroinstruction is either a simple macroinstruction comprising the first microinstruction or a complex macroinstruction comprising several microinstructions of which the first microinstruction is an initial microinstruction that is equivalent to the simple macroinstruction;
• a second microcode generator coupled to receive the entry point value, the second microcode generator for generating a second microinstruction vector in response to the entry point value;
• and
• a sequencing circuit coupled to receive the first microinstruction vector and the second microinstruction vector, the sequencing circuit for sequentially outputting the first microinstruction vector and the second microinstruction, the sequencing circuit comprising:
• a first signal generator coupled to the decode circuit and the first microcode generator, the first signal generator for generating a first signal indicating that the first microcode generator has the first microinstruction vector to transfer, wherein the first signal is generated in response to the first microinstruction vector being generated;
• a second signal generator coupled to the decode circuit and the second microcode generator, the second signal generator for generating a second signal indicating that the second microcode generator has the second microinstruction vector to transfer if the entry value is received from the decode circuit;
• a multiplexer coupled to receive the first and second microinstruction vectors, the multiplexer for selectively outputting a one of the first and second microinstruction vectors in response to a control signal, wherein the multiplexer outputs the first microinstruction vector when the control signal is in a first state and the second microinstruction vector when the control signal is in a second state, the multiplexer being disabled when the control signal is in a third state;
• a control signal generator coupled to the multiplexer and the first and second signal generators, the control signal generator for generating the control signal.