Prolog interrupt processing
AssigneeInternational Business Machines Corporation
InventorMarc J. L. Gillet
Life of this patent
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Abstract
An improved architecture for a Prolog interpreter/compiler is described to facilitate interrupt processing. The new architecture employs interrupt control words and a set of interrupt control blocks to enhance Prolog processing. As interrupts are detected, an interrupt control word is loaded with the address of an interrupt control block for managing interrupt processing. Then, each time a new predicate is fired, the interrupt control word is tested and control is passed to the interrupt processing routine if the control word is non-zero.
Claims17
A method for operating a computer system to process a predicate associated with an interrupt when the interrupt occurs during the processing of another predicate, comprising the steps of:
- (a) commencing processing of a first predicate;
- (b) detecting the occurrence of an interrupt associated with a second predicate;
- (c) storing interrupt information, further comprising the steps of
- (i) determining whether the interrupt is sensitive to backtracking,
- (ii) storing data indicative of backtracking sensitivity, and
- (iii) storing data indicative of the occurrence of the interrupt and the second predicate;
- (d) completing processing of the first predicate;
- and
- (e) processing the second predicate using the interrupt information.
A method for operating a computer system having common storage to process a predicate associated with an interrupt when the interrupt occurs during the processing of another predicate, comprising the steps of:
- (a) commencing processing of a first predicate;
- (b) detecting the occurrence of an interrupt associated with a second predicate;
- (c) storing in the common storage interrupt control block information, further comprising the steps of
- (i) determining whether the interrupt is sensitive to backtracking,
- (ii) storing data indicative of backtracking sensitivity, and
- (iii) storing data indicative of the second predicate's predicate descriptor and arguments;
- (d) storing in the common storage interrupt flag information indicative of the occurrence of the interrupt and the location of the interrupt control block;
- (e) completing processing of the first predicate;
- (f) reading the interrupt flag to ascertain the location of the interrupt control block;
- (g) reading the interrupt control block from the common storage to ascertain the location of the second predicate's predicate descriptor and arguments;
- and
- (h) processing the second predicate.
A computerized system for processing a predicate associated with an interrupt when the interrupt occurs during the processing of another predicate, comprising:
- (a) means for commencing processing of a first predicate;
- (b) means for detecting the occurrence of an interrupt, the interrupt being associated with a second predicate;
- (c) means for storing interrupt information comprising
- (i) means for determining whether the interrupt is sensitive to backtracking,
- (ii) means for storing data indicative of backtracking sensitivity, and
- (iii) means for storing data indicative of the occurrence of the interrupt and the second predicate;
- (d) means for completing processing of the first predicate;
- and
- (e) means for processing the second predicate using the interrupt information.
Dependencies are inferred from the claim text.