Register address specifying circuit for simultaneously accessing two registers

A data processor that allows first and second data words to be simultaneously transferred between first and second registers of a register file and a memory in response to a macroinstruction that transfers a plurality of data words between the memory and the register file, said data processor comprising:

• instruction decoding means for decoding, from said macroinstruction, a first microinstruction and a second microinstruction;
• and
• instruction executing means, including:
• a data register for holding the first and second data words;
• a first bus for transferring the first data word to said data register from the first register;
• a second bus for transferring the second data word to said data register from the second register;
• a register address specifying circuit having a decoding control circuit for decoding a binary address N of a register into a first bit string and for shifting said first bit string M bits to obtain a second bit string, and a selector, coupled to said decoding control circuit, to which said first bit string and said second bit string are input, for selectively outputting said first bit string to access a register having an address N and said second bit string to access a register having an address either N+M or N-M;
• said instruction executing means for executing said first microinstruction so that said register address specifying circuit accesses the first register according to said first bit string to transfer the first data word from the first register to said data register and for executing said second microinstruction so that said register address specifying circuit accesses the first register according to said first bit string to transfer said first data word to said data register from the first register, and simultaneous to accessing the first register, accesses the second register according to said second bit string to transfer said second data word to said data register from the second register, thereby joining the first data word and the second data word for transfer to the memory.

A data processor that allows first and second data words to be simultaneously transferred between first and second registers of a register file and a memory in response to a macroinstruction that transfers a plurality of data words between the memory and the register file, said data processor comprising:

• instruction decoding means for decoding, from said macroinstruction, a first microinstruction and a second microinstruction;
• and
• instruction executing means, including:
• a data register for holding the first and second data words transferred from the memory;
• a first bus for transferring the first data word to the first register from said data register;
• a second bus for transferring the second data word to the second register from said data register;
• a register address specifying circuit having a decoding control circuit for decoding a binary address N of a register into a first bit string and for shifting said first bit string M bits to obtain a second bit string, and a selector, coupled to said decoding control circuit, to which said first bit string and said second bit string are input, for selectively outputting said first bit string to access a register having an address N and said second bit string to access a register having an address either N+M or N-M;
• said instruction executing means for executing said first microinstruction so that said register address specifying circuit accesses the first register according to said first bit string to transfer the first data word from said data register to the first register and for executing said second microinstruction so that said register address specifying circuit accesses the first register according to said first bit string to transfer said first data word from said data register to the first register, and simultaneous to accessing the first register, accesses the second register according to said second bit string to transfer said second data word from said data register to the second register.