Method and apparatus for accessing variable length words in a memory array

An apparatus for decoding an address to access a word in a memory space, said memory space being arranged as a matrix of rows and columns and being capable of storing words of various widths comprising;

• an address generator for generating an address of a selected word in said memory space, said address comprising at least I+J bits, where I and J are integers,
• a word width generator for generating a signal indicating the width of the word being accessed,
• a plurality of M-bit wide switches coupled between an M-bit wide columnar portion of said memory space and an M-bit wide portion of a bus, where M is an integer,
• a row decoder for indicating a row of said matrix by decoding I bits of said address,
• a column decoder having an output coupled to control said switches for indicating appropriate ones of said switches responsive to said J bits of the address and said word length indicator signal, said column decoder comprising;
• a plurality of sub-decoders, each sub-decoder corresponding to a word width which is storable in said memory space, each sub-decoder asserting a column output signal identifying a columnar portion of the memory space responsive to said J bits of said address, the width of said columnar portion being equal to the corresponding word width,
• a multiplexer for selecting and outputting to said switches the column signal of one of the sub-decoders responsive to the word width indicator signal, and wherein said switches selectively provide a communication link between said bits of said memory space indicated by said row and column decoders and the corresponding portion of said bus when said switches are activated.