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US 5,396,605 AGranted
Buffer storage control apparatus including a translation lookaside buffer and an improved address comparator layout arrangement
AssigneeHitachi, Ltd.
InventorHideo Sawamoto
Life of this patent
Estimating the term…
Abstract
A buffer storage control apparatus includes a plurality of sets of buffer address arrays, each of the sets storing the same content and being allocated to one of a plurality of rows of a translation look-aside buffer. With this arrangement, it is possible to reduce the length of wiring lines leading from the translation look-aside buffer to the buffer address arrays and to minimize intersections of the wiring lines, thereby reducing signal delays.
Claims18
A buffer storage control apparatus comprising:
- a translation lookaside buffer including m (where m.gtoreq.2) rows forming a virtual storage system;
- a buffer address array including m sets of n (where n.gtoreq.1) rows forming a buffer storage system, corresponding buffer locations in each set of said m sets of n rows of said buffer address array storing a same content;
- and
- m sets of n comparator circuits, each set of m sets of n comparator circuits being provided for a corresponding group of a respective set of said m sets of n rows of said buffer address array and a respective one row of said m rows of said translation lookaside buffer, for comparing n outputs of each set of said m sets of n rows of said buffer address array with corresponding m outputs of said respective one row of said m rows of the translation lookaside buffer.
1 more element
An address comparing apparatus, comprising:
- m (where m.gtoreq.2) translation lookaside RAM (random access memory) devices for storing m translation sets of first addresses;
- m sets of n (where n.gtoreq.1) buffer address RAM devices, each buffer set of said m sets of n buffer address RAM devices corresponding to a respective translation set of said m translation sets of said m translation lookaside RAM devices and storing n sets of second addresses to be compared with said first addresses stored in a corresponding one of said m translation lookaside RAM devices, each buffer set of said m sets of n buffer address RAM devices having respective storage locations corresponding to respective storage locations of other buffer sets of said m sets of n buffer address RAM devices and storing a same content;
- and
- m sets of n comparator circuits, each set of said m sets of n comparator circuits corresponding to a corresponding group of a respective buffer set of said n buffer address RAM devices and a respective translation set of said m translation lookaside RAM devices and comparing n outputs of corresponding n buffer address RAM devices with an output of a corresponding translation set of said m translation lookaside RAM devices.
1 more element
An integrated circuit including an address comparing apparatus, comprising:
- m (where m.gtoreq.2) translation lookaside RAM (random access memory) devices for storing m translation sets of first addresses;
- m sets of n (where n.gtoreq.1) buffer address RAM devices, each buffer set of said m sets of n buffer address RAM devices corresponding to a respective translation lookaside RAM of said m translation lookaside RAM devices, and storing n sets of second addresses to be compared with said first addresses stored in a corresponding translation lookaside RAM device of said m translation lookaside RAM devices;
- and
- m sets of n comparator circuits, each set of said m sets of n comparator circuits corresponding to a corresponding group of a respective buffer set of said m sets of n buffer address RAM devices and a respective translation lookaside RAM device of said m translation lookaside RAM devices and comparing n outputs of corresponding n buffer address RAM devices with an output of a corresponding said translation lookaside RAM device of said m translation lookaside RAM devices;
- wherein said integrated circuit has a plurality of corresponding groups, each comprised of one of said m translation lookaside RAM devices, n of said buffer address RAM devices, and n of said comparator circuits, said corresponding groups being arranged separately from one another on said integrated circuit to avoid any crossing of connecting lines leading from said translation lookaside RAM devices and said buffer address RAM devices to said comparator circuits.
2 more elements
Dependencies are inferred from the claim text.