System and method for reducing the penalty associated with data cache misses

A computer system having a central processor unit (CPU) with a reduced instruction set, a decoder and a data cache memory, the system adapted to service a data cache miss in parallel with normal instruction execution to thereby reduce or avoid the penalty associated with a data cache miss, comprising the steps of:

• first means for decoding a first instruction that requires a load to a read only register, wherein said first instruction provides a hint to the data cache memory to prefetch a cache line from a main memory into the data cache memory, wherein said load to said read only register does not alter the contents of said read only register;
• and
• second means for processing, substantially simultaneously with said prefetch of said cache line, further instructions following said first instruction;
• whereby said first instruction allows said cache line to be prefetched from said main memory early enough so that subsequent accesses to this data will not result in a data cache miss.

In a computer system having a data cache memory, a method for reducing or avoiding the penalty associated with a data cache miss, comprising the steps of:

• (1) executing a first load instruction that requires a load to a read only register, said first load instruction functions as a hint to prefetch a cache line from memory, wherein said load to said read only register does not alter the contents of said read only register;
• (2) executing a stream of instructions following said load instruction, wherein the processing of said prefetch is done in parallel with said executing of said stream of instructions;
• (3) executing a second load instruction that uses dam from said cache line fetched from memory;
• wherein said first load instruction is placed within said stream of instructions to allow the system to retrieve said cache line early enough so that the data will be available when it is actually needed by said second load instruction.