US 5,396,602 A · Arbitration logic for multiple bus computer system

Abstract

An arbitration mechanism is provided for use in a computer system which comprises (i) a central processing unit (CPU); (ii) a first system bus which connects the CPU to system memory so that the CPU can read data from, and write data to, the system memory; (iii) a second system bus connected to the CPU; (iv) a host bridge connecting the second system bus to a peripheral bus, the peripheral bus having at least one peripheral device attached thereto; and (v) an input/output (I/O) bridge connecting the peripheral bus to a standard I/O bus, the standard I/O bus having a plurality of standard I/O devices attached thereto. The arbitration mechanism comprises (i) a first level of logic for arbitrating between the plurality of standard I/O devices, wherein one standard I/O device is selected from a plurality of the standard I/O devices competing for access to the standard I/O bus, and (ii) a second level of logic for arbitrating between the selected standard I/O device, the CPU and the at least one peripheral device, wherein one of the selected standard I/O device, the CPU and the at least one peripheral device is selected to access the peripheral bus. The arbitration mechanism includes sideband signals which connect the first and second levels of arbitration logic and include arbitration identification information corresponding to the selected standard I/O device.

Claims20

Dependent claims

An information processing system, comprising:

a central processing unit (CPU);
a first system bus which connects said CPU to a system memory so that said CPU can read data from, and write data to, said system memory;
a second system bus connected to said CPU;
a host bridge connecting said second system bus to a peripheral bus, said peripheral bus having at least one peripheral device attached thereto;
an input/output (I/O) bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus provided with a connector to which may be attached a plurality of standard I/O devices each of which corresponds to an individual I/O bus location;
and
bi-level arbitration logic electrically connected to said second system bus, said bi-level arbitration logic comprising (i) a first level of logic for performing arbitration on said I/O bus, wherein one of said individual I/O bus locations is selected from a plurality of said individual I/O bus locations competing for access to said standard I/O bus, and (ii) a second level of logic for arbitrating between said selected individual I/O bus location, said CPU and said at least one peripheral device, wherein one of said selected individual I/O bus location, said CPU and said at least one peripheral device is selected to access said peripheral bus;
and
wherein said bi-level arbitration logic includes sideband signals directly connecting said first and second levels of arbitration logic, said sideband signals including arbitration identification information corresponding to said selected individual I/O bus location.

6 more elements

An arbitration mechanism for use in a computer system which comprises (i) a central processing unit (CPU);

(ii) a first system bus which connects said CPU to a system memory so that said CPU can read data from, and write data to, said system memory;
(iii) a second system bus connected to said CPU;
(iv) a host bridge connecting said second system bus to a peripheral bus, said peripheral bus having at least one peripheral device attached thereto;
and (v) an input/output (I/O) bridge connecting said peripheral bus to a standard I/O bus, said standard I/O bus provided with a connector to which may be attached a plurality of standard I/O devices each of which corresponds to an individual I/O bus location, said arbitration mechanism being electrically connected to said second system bus and comprising:
(i) a first level of logic for performing arbitration on said I/O bus, wherein one of said individual I/O bus locations is selected from a plurality of said individual I/O bus locations competing for access to said standard I/O bus, and (ii) a second level of logic for arbitrating between said selected individual I/O bus location, said CPU and said at least one peripheral device, wherein one of said selected individual I/O bus location, said CPU and said at least one peripheral device is selected to access said peripheral bus;
and
wherein said arbitration mechanism includes sideband signals directly connecting said first and second levels of arbitration logic, said sideband signals including arbitration identification information corresponding to said selected individual I/O bus location.

4 more elements

Dependencies are inferred from the claim text.

Arbitration logic for multiple bus computer system

Life of this patent

Arbitration logic for multiple bus computer system

Life of this patent

Abstract

Claims20