Microprocessor system having a single, common internal bus transferring data and instructions in different states of a machine cycle

A CPU core for a single chip microcomputer, the CPU core being connectable to on-chip circuits peripheral to the CPU core via one or more buses, the CPU core being operable to read or write signals onto or from one bus interconnected to another bus without affecting the other bus, comprising:

• a peripheral bus connected to a peripheral circuit for communicating digital signals between the CPU core and the peripheral circuit;
• a single chip microcomputer CPU core including an internal bus, an arithmetic and logic unit, and an accumulator all connected to said internal bus;
• the CPU core further including a bus control circuit coupled to said internal bus and said peripheral bus, said bus control circuit including a plurality of interface circuit portions;
• each interface circuit portion comprising:
• a latch circuit having an input and an output, said latch input being connected to a corresponding line forming part of said internal bus,
• a logic circuit having a first input coupled to said latch output and having a second input coupled to receive a precharge timing signal;
• a driver circuit having an output coupled to a corresponding line of said peripheral bus and having an input coupled to the output of said logic circuit;
• a selectively operable circuit coupling said corresponding line of said peripheral bus to the corresponding line of the internal bus;
• said interface circuit portions being configured so that said bus control circuit may be operated to receive a precharge signal and in response thereto, precharge the lines of the peripheral bus during a precharging period, then data may be communicated from the peripheral circuit via the peripheral bus to the interface circuit portions, with the circuit interface portion then selectively coupling the signals from the peripheral bus to the internal bus;
• whereby the precharging signal may be applied to the peripheral bus without disturbing the internal bus.