Image signal interpolating circuit for calculating interpolated values for varying block sizes

An image signal decoding apparatus comprising:

• an image signal interpolating circuit comprising a plurality of integrated circuits, each integrated circuit including:
• a first memory, second memory, third memory and fourth memory for storing pixel data of 2.times.2 pixels, with each of the first, second, third and fourth memories storing pixel data of at least one pixel;
• an interpolative operation circuit for calculating interpolated values on the basis of respective pixel data of 2.times.2 pixels stored in the first, second, third and fourth memories;
• and
• control means for controlling input of the pixel data to the integrated circuit and output of interpolated values from the integrated circuit and pixel data from the first, second, third and fourth memories;
• a reading circuit for reading image data and motion vector information from a memory medium,
• a frame memory for storing image data read from the memory medium;
• connecting means for connecting the plurality of integrated circuits to the frame memory so that the integrated circuits are arrayed to calculate interpolated values between respective pixels of a block comprised of pixels of x.times.m pixels (where n and m are positive integers);
• a detector for detecting the motion vector information;
• and
• a control circuit for generating control signals for the frame memory and the image signal interpolating circuit on the basis of motion vector information from the detector, thus to decode image data from the frame memory by the image signal interpolating circuit.