Method and apparatus for clock synchronization with information received by a radio receiver

A radio receiver for receiving a radio frequency signal, the radio receiver comprising:

• a receiver circuit for generating from the radio frequency signal a data signal having alternating first and second edges;
• a clock for generating a clock signal having a clock period;
• and
• adjusting means for adjusting the clock period on one of the first edges of the data signal by increasing the clock period when the clock signal is late with respect to the data signal and by decreasing the clock period when the clock signal is early with respect to the data signal;
• first inhibiting means for inhibiting adjustment of the clock period on one of the second edges of the data signal following the one of the first edges when the clock signal is early with respect to the data signal and when, on the one of the first edges of the data signal, the clock period was increased;
• and
• second inhibiting means for inhibiting adjustment of the clock period on the one of the second edges of the data signal when the clock signal is late with respect to the data signal and when, on the one of the first edges of the data signal, the clock period was decreased.

A radio receiver for receiving a radio frequency signal, the radio receiver comprising:

• a receiver circuit for generating from the radio frequency signal a data signal having alternating first and second edges;
• a clock for generating a clock signal having a clock period;
• a synchronization circuit coupled to the clock and the receiver circuit for generating information by which the clock signal can be synchronized to the data signal, wherein the synchronization circuit comprises:
• adjusting means for indicating, on one of the first edges of the data signal, that the clock period should be increased when the clock signal is late with respect to the data signal and by decreasing the clock period when the clock signal is early with respect to the data signal;
• first inhibiting means for indicating, on one of the second edges of the data signal following the one of the first edges, that adjustment of the clock period should be inhibited when the clock signal is early with respect to the data signal and when, on the one of the first edges of the data signal, the clock period was increased;
• and
• second inhibiting means for indicating, on the one of the second edges of the data signal following the one of the first edges, that adjustment of the clock period should be inhibited when the clock signal is late with respect to the data signal and when, on the one of the first edges of the data signal, the clock period was decreased;
• and
• a phase-locked loop coupled to the synchronization circuit and the clock for increasing and decreasing the clock signal in accordance with the information provided by the synchronization circuit.