Local area network bridge apparatus with dedicated packet filtering mechanism

A local area network (LAN) bridge apparatus for packet filtering packets transmitted from a LAN, comprising:

• filtering address table (FAT) memory means having a plurality of entries for registering FAT data, each FAT data containing a filtering address (FA);
• FAT memory address generation means for generating FAT memory addresses for specifying the entries of the FAT memory means by compressing one of a sender address (SA) and a destination address (DA) of each packet transmitted from the LAN;
• address learning means for obtaining the SA of each packet transmitted from the LAN, and registering the FAT data with the obtained SA as the FA In one of the entries of the FAT memory means specified by the FAT memory address generated by the FAT memory address generation means from the SA of said each packet;
• DA obtaining means for obtaining a DA from each packet transmitted from the LAN;
• judging means for judging a packet transmitted from the LAN as a packet to be discarded when the FA of the FAT data registered in one of the entries of the FAT memory means specified by the FAT memory address generated by the FAT memory address generation means from the DA of said packet coincides with the DA obtained by the DA obtaining means from said packet;
• a LAN controller for discarding said packet judged as a packet to be discarded by the judging means, and receiving a packet transmitted from the LAN which is not judged as a packet to be discarded by the judging means;
• and
• a micro-processor for controlling the LAN controller to relay each packet received by the LAN controller to another LAN;
• wherein the FAT memory address generation means comprises a cyclic redundant check (CRC) circuit and the micro-processor specifies compression data used at the FAT memory address generation means in compressing one of the SA and the DA of each packet transmitted from the corresponding one of said at least two LANs in a form of a generator-polynomial.

A local area network (LAN) bridge apparatus for stripping of packets transmitting in a ring type LAN, comprising:

• filtering address table (FAT) memory means having a plurality of entries for registering FAT data, each FAT data containing a filtering address (FA);
• FAT memory address generation means for generating FAT memory addresses for specifying the entries of the FAT memory means by compressing a sender address (SA) of each packet transmitting in the ring type LAN;
• address learning means for obtaining the SA of each packet transmitted into the ring type LAN, and registering the FAT data with the obtained SA as the FA in one of the entries of the FAT memory means specified by the FAT memory address generated by the FAT memory address generation means from the SA of said each packet;
• SA obtaining means for obtaining a SA from each packet transmitting in the ring type LAN;
• judging means for judging a packet transmitting in the ring type LAN as a packet to be stripped when the FA of the FAT data registered in one of the entries of the FAT memory means specified by the FAT memory address generated by the FAT memory address generation means from the SA of said packet coincides with the SA obtained by the SA obtaining means from said packet;
• a LAN controller for stripping said packet judged as a packet to be stripped by the judging means;
• and
• a micro-processor for controlling the LAN controller to relay each packet received by the LAN controller;
• wherein the FAT memory address generation means comprises a cyclic redundant check (CRC) circuit and the micro-processor specifies compression data used at the FAT memory address generation means in compressing the SA of each packet transmitted from the corresponding one of said at least two LANs in a form of a generator polynomial.

A local area network (LAN) bridge apparatus for interfacing at least two LANs, comprising:

• at least one filtering address table (FAT) memory means having a plurality of entries for registering FAT data, each FAT data containing a filtering address (FA);
• at least two filtering control units provided in correspondence to said at least two LANs, each filtering control unit including:
• FAT memory address generation means for generating FAT memory addresses for specifying the entries of the FAT memory means by compressing one of a sender address (SA) and a destination address (DA) of each Packet transmitted from a corresponding one of said at least two LANs;
• address learning means for obtaining the SA of each packet transmitted from the corresponding one of said at least two LANs, and registering the FAT data with the obtained SA as the FA in one of the entries of the FAT memory means specified by the FAT memory address generated by the FAT memory address generation means from the SA of said each packet;
• DA obtaining means for obtaining a DA from each packet transmitted from the corresponding one of said at least two LANs;
• and
• judging means for judging a packet transmitted from the corresponding one of said at least two LANs as a packet to be discarded when the FA of the FAT data registered in one of the entries of the FAT memory means specified by the FAT memory address generated by the FAT memory address generation means from the DA of said packet coincides with the DA obtained by the DA obtaining means from said packet;
• at least two LAN controllers provided in correspondence to said at least two filtering control units, for discarding said packet judged as a packet to be discarded by the judging means of a corresponding one of said at least two filtering control units, and receiving a packet transmitted from the corresponding one of said at least two LANs which is not judged as a packet to be discarded by the judging means of the corresponding one of said at least two filtering control units;
• and
• a micro-processor for controlling each of said at least two LAN controllers to relay each packet received by each of said at least two LAN controllers to the LANs other than the corresponding one of said at least two LANs;
• wherein said at least one FAT memory means comprises only one FAT memory means shared by said at least two filtering control units.