Method and apparatus for adaptive clock recovery

In an arrangement comprising:

• means for receiving asynchronous transfer mode, packetized information,
• means for storing said received information and
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency,
• a method comprising
• continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value,
• detecting an increasing condition of said monitored deviation and
• in response to said detected increasing condition, adjusting said adaptive line clock frequency but without continually adjusting said adaptive line clock frequency in response to said monitored deviation.

In an arrangement comprising:

• means for receiving asynchronous transfer mode, packetized information,
• means for storing said received information and
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency,
• a method comprising
• continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value,
• continually determining an apparent source frequency,
• detecting an increasing condition of said monitored deviation and
• in response to said detected increasing condition, adjusting said adaptive line clock frequency based in part on said continually determined apparent source frequency.

In an arrangement comprising:

• means for receiving asynchronous transfer mode, packetized information,
• means for storing said received information and
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency,
• a method comprising
• continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value,
• continually determining an apparent source frequency based on said monitored deviation and said adaptive line clock frequency for use in adjusting said adaptive line clock frequency.

In an arrangement comprising:

• means for receiving asynchronous transfer mode, packetized information,
• means for storing said received information and
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency,
• a method comprising
• continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value,
• detecting an increasing condition of said monitored deviation and
• in response to said detected increasing condition, performing open-loop adjustment of said adaptive line clock frequency.

Adaptive clock recovery apparatus comprising

• means for receiving asynchronous, packetized information,
• means for storing said received information,
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, (b) detecting an increasing condition of said monitored deviation, and (c) in response to said detected increasing condition, adjusting said adaptive line clock frequency but without continually adjusting said adaptive line clock frequency in response to said monitored deviation.

Adaptive clock recovery apparatus comprising

• means for receiving asynchronous, packetized information,
• means for storing said received information,
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, (b) detecting an increasing condition of said monitored deviation, and (c) in response to said detected increasing condition, performing open-loop adjustment of said adaptive line frequency.

An interface between an ATM cell stream and a synchronous circuit line stream comprising

• means for receiving said ATM cell stream,
• means for extracting header information from said received ATM cell stream to obtain payload information,
• means for storing said payload information,
• means for serially transmitting said stored payload information on said synchronous circuit line stream in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, (b) detecting an increasing condition of said monitored deviation, and (c) in response to said detected increasing condition, adjusting said adaptive line clock frequency in a plurality of modes.

An interface between an ATM cell stream and a synchronous circuit line stream comprising

• means for receiving said ATM cell stream,
• means for extracting header information from said received ATM cell stream to obtain payload information,
• means for storing said payload information,
• means for serially transmitting said stored payload information on said synchronous circuit line stream in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, (b) detecting an increasing condition of said monitored deviation, and (c) in response to said detected increasing condition, adjusting said adaptive line clock frequency but without continually adjusting said adaptive line clock frequency in response to said monitored deviation.

An interface between an ATM cell stream and a synchronous circuit line stream comprising

• means for receiving said ATM cell stream,
• means for extracting header information from said received ATM cell stream to obtain payload information,
• means for storing said payload information,
• means for serially transmitting said stored payload information on said synchronous circuit line stream in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, (b) continually determining an apparent source frequency, (c) detecting an increasing:
• condition of said monitored deviation, and (d) in response to said detected increasing condition, adjusting said adaptive line clock frequency based in pan on said continually determined apparent source frequency.

An interface between an ATM cell stream and a synchronous circuit line stream comprising

• means for receiving said ATM cell stream,
• means for extracting header information from said received ATM cell stream to obtain payload information,
• means for storing said payload information,
• means for serially transmitting said stored payload information on said synchronous circuit line stream in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, and (b) continually determining an apparent source frequency based on said monitored deviation and said adaptive line clock frequency for use in adjusting said adaptive line clock frequency.

An interface between an ATM cell stream and a synchronous circuit line stream comprising

• means for receiving said ATM cell stream,
• means for extracting header information from said received ATM cell stream to obtain payload information,
• means for storing said payload information,
• means for serially transmitting said stored payload information on said synchronous circuit line stream in response to an adaptive line clock frequency, and
• processor means for (a) continually monitoring the deviation in the magnitude of information stored in said storing means from a nominal value, and (b) performing open-loop adjustment of said adaptive line clock frequency.

Adaptive clock recovery apparatus comprising:

• means for receiving asynchronous, packetized information,
• means for storing said received information,
• means for determining a magnitude of information stored in said storing means connected to said storing means,
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency, and
• a processor controlled by a stored program to continually monitor the deviation in the magnitude of information from said determining means from a nominal value and continually determine an apparent source frequency based on said monitored deviation and said adaptive line clock frequency for adjusting said adaptive line clock frequency.

Adaptive clock recovery apparatus comprising:

• means for receiving asynchronous, packetized information,
• means for storing said received information,
• means for determining a magnitude of information stored in said storing means connected to said storing means,
• means for transmitting said stored information on a synchronous circuit in response to an adaptive line clock frequency, and
• a processor controlled by a stored program to continually monitor the deviation in the magnitude of information from said determining means from a nominal value, detect an increasing condition of said monitored deviation, and perform an open-loop adjustment of said adaptive line frequency in response to said increasing condition.

An interface between an ATM cell stream and a synchronous circuit line stream comprising

• means for receiving said ATM cell stream,
• means for extracting header information from said received ATM cell stream to obtain payload information,
• means for storing said payload information,
• means for determining a magnitude of information stored in said storing means connected to said storing means,
• means for serially transmitting said stored payload information on said synchronous circuit line stream in response to an adaptive line clock frequency, and
• a processor controlled by a stored program to continually monitor the deviation in the magnitude of information from said determining means from a nominal value, detect an increasing condition of said monitored deviation, and adjust said adaptive line clock frequency in a plurality of modes in response to said detected increasing condition.