Monolithically integrated data memory arrangement and method for the operation thereof
AssigneeSiemens Aktiengesellschaft
InventorRainer Storn
Life of this patent
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Abstract
In a memory arrangement and operating method therefor which enables an accelerated table search, an address generator, which operates according to a hash method, and an addressable memory are, integrated on a chip. A further advantage is achieved when the address generator is programmable, so that the hash method can be variably prescribed. A further acceleration is achieved when a CRC method is utilized for the calculation of the hash addresses and when intermediate results of the polynomial division are stored in tables. Two advantages are thus exploited. One advantage is an increase in speed due to the integration, and the further advantage is an increase in speed due to the accelerated polynomial division, as well as the high access hit rates inherent in the hash method.
Claims5
Method for operating a monolithically integrated data memory arrangement, comprising the steps of:
- providing at least one addressable main memory area for acceptance of data to be stored in at least one memory;
- providing at least one address generator which generates at least one address for addressing the main memory area from data to be stored, and producing said at least one address by applying a hash function onto at least a part of the data to be stored;
- and
- using a polynomial division on the basis of a generator polynomial, as said hash function.
A monolithically integrated data memory arrangement, comprising:
- at least one addressable main memory area for acceptance of data to be stored in at least one memory;
- at least one address generator which generates at least one address for addressing the main memory area from data to be stored, said at least one address generator producing said at least one address by applying a hash function onto at least a part of the data to be stored;
- at least one data gate logic which, dependent on at least one control signal, controls access onto the memory in write and read events in that said at least one data gate logic either reads in data pending at a bus or reads out data pending at the memory;
- and
- at least one status logic which, dependent on at least one further control signal, controls a data word length to be handled by said at least one data gate logic.
Dependencies are inferred from the claim text.