Data output circuit of a semiconductor memory device

A data output circuit of a semiconductor memory circuit with pull-up and pull-down transistors to respectively receive through gates of said pull-up and pull-down transistors a pair of signals having complementary logic levels, comprising:

• first and second pre-charge means for respectively pre-charging input levels of a pair of data signals read from a memory cell up to a source voltage level in the disabling of data output;
• first and second switching means for respectively amplifying and connecting output signals of said first and second pre-charge means to said gates of said pull-up and pull-down transistors;
• first and second enable circuits for respectively connecting output signals of said first and second switching means to said gates of said pull-up and pull-down transistors in the enabling of the data output;
• wherein said first and second switching means are level change circuits for respectively controlling said pull-up and pull-down transistors by employing a constant voltage source to provide a voltage rise (Vpp) increased over said source voltage level before enabling data output.

A data output circuit of a semiconductor memory circuit with pull-up and pull-down transistors to respectively receive through gates of said pull-up and pull-down transistors a pair of signals having complementary logic levels, comprising:

• first and second pre-charge means for respectively pre-charging input levels of a pair of data signals read from a memory cell up to a source voltage level in the disabling of data output;
• first and second switching means for respectively amplifying and connecting output signals of said first and second pre-charge means to said gates of said pull-up and pull-down transistors;
• first and second enable circuits for respectively connecting output signals of said first and second switching means to said gates of said pull-up and pull-down transistors in the enabling of the data output;
• wherein said first and second pre-charge means are driven by a control signal generated from an address transition circuit provided in said memory circuit, said control signal enabling said data signals read from said memory cell to be inputted to said data output circuit in a data output mode.