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US 5,396,462 AGranted
Semiconductor memory device having a data-lines clamp circuit
AssigneeNEC Corporation
InventorTomoyuki Kaneko
Life of this patent
Estimating the term…
Abstract
Diodes are connected between a clamp control line and respective one of data lines. A voltage of the clamp control line in a read operation is set to a value higher, by a forward voltage of the diodes or less, than a lower value among the voltages of the data line to which a selected digit line is connected. The voltages of the data lines to which only non-selected digit lines are connected are clamped to a predetermined value.
Claims12
A semiconductor memory device, comprising:
- a plurality of digit line pairs, a plurality of cells being coupled to each digit line pair, each digit line pair transmitting read signals from a selected memory cell;
- at least two pairs of data lines, each data line pair being provided for every plurality of digit line pairs;
- selecting means coupled to the plurality of digit line pairs and the at least two pairs of data lines for receiving address signals and for selecting one of the digit line pairs in response to the address signals and transmitting signals on the selected digit line pair to a corresponding data line pair;
- sense amplifier means coupled to the plurality of data line pairs and for detecting and outputting voltages of the data line pairs to which the signals on the selected digit line pair are transmitted;
- and
- clamp means comprised of diodes, anodes of which receiving a predetermined clamp reference voltage, and each of the cathodes of which being coupled to a corresponding one of said data lines, for clamping voltages of the data lines corresponding to only non-selected digit line pairs at a predetermined voltage.
3 more elements
A semiconductor memory device, comprising:
- a plurality of digit line pairs, a plurality of memory cells being coupled to each digit line pair, each digit line pair transmitting read signals from selected memory cell;
- at least two pairs of data lines, each data line pair being provided for every plurality of digit line pairs;
- selecting means coupled to the plurality of digit line pairs and the at least two pairs of data lines for receiving address signals and for selecting one of the digit line pairs in response to the address signals and transmitting signals on the selected digit line pair to corresponding one of the data line pairs;
- sense amplifier means coupled to the plurality of data line pairs and for detecting and outputting voltages of the data line pairs to which the signals on the selected digit lines pair are transmitted;
- and
- clamp means comprised of bipolar transistors bases of which receiving a predetermined clamp reference voltage and emitters of which being coupled to corresponding one of the data lines, and collectors of which receiving a predetermined voltages, for clamping a voltages of the data lines corresponding to only non-selected digit line pairs to a predetermined voltage.
3 more elements
A semiconductor memory device, comprising:
- a plurality of first digit line pairs, a plurality of memory cells being coupled to each of the first digit line pairs;
- a plurality of second digit line pairs, a plurality of memory cells being coupled to each of the second digit line pairs;
- a first data line pair;
- a second data line pair;
- switching means for selecting one of the first and second digit line pairs and for coupling the selected digit line pair to the first or second data line pair;
- means, coupled to the first and second data line pairs, for sensing, amplifying and outputting the signals on the first or second data line pair;
- and
- diodes, anodes of which receiving a predetermined clamp reference voltage and cathodes of which being coupled to the corresponding one of the first and second data lines.
5 more elements
A semiconductor memory device, comprising:
- a plurality of first digit line pairs, a plurality of memory cells being coupled to each of the first digit line pairs;
- a plurality of second digit line pairs, a plurality of memory cells being coupled to each of the second digit line pairs;
- a first data line pair;
- a second data line pair;
- switching means for selecting one of the first and second digit line pairs and for coupling the selected digit line pair to the first or second data line pair;
- means, coupled to the first and second data line pairs, for sensing, amplifying, and outputting the signals on the first or second data line pair;
- and
- clamp means comprised of bipolar transistors bases of which receiving a predetermined clamp reference voltage, each emitter being coupled to corresponding one of first and second data lines, and a collector of which receiving a predetermined voltage.
5 more elements
Dependencies are inferred from the claim text.