Single transistor flash electrically programmable memory cell in which a negative voltage is applied to the nonselected word line
AssigneeSony Corporation
InventorHideki Arakawa
Life of this patent
Estimating the term…
Abstract
A nonvolatile semiconductor memory using a single floating gate transistor, wherein a control gate elecrrode is negatively biased while a source region is positively biased, and a writing operation is performed bit by bit by transferring electrons from the floating gate into the source region through Fowler-Nordheim tunneling. And an erasing operation is performed by injecting channel hot electrons from the drain region into the floating gate, or by injecting electrons from a substrate into the floating gate through Fowler-Nordheim tunneling. The source region is connected to an individual bit line, and the drain region to a common line so that over-erasing is averted.
Claims17
An array of flash EEPROM memory cells wherein each memory cell is programmable by injecting electrons into its floating gate and wherein a negative voltage is applied to the nonselected word line of said array in a reading operation.
An array of flash EEPROM memory cells wherein each memory cell is programmable by injecting electrons into its floating gate and wherein a negative voltage is applied to the nonselected word line of said array in a reading operation, further comprising a word line decoding circuit comprising:
- a first power supply terminal and a second power supply terminal, wherein a potential applied to said first power supply terminal is greater than a potential applied to said second power supply terminal in said reading operation or in a writing operation and a potential applied to said second power supply terminal is greater than a potential applied to said first power supply terminal in an erasing operation;
- a level conversion circuit comprising a pair of inverters whose input and output terminals are cross coupled to each other;
- and
- a transfer gate having a terminal coupled to an output of said word line decoding circuit and another terminal coupled to an input/output terminal of said level conversion circuit.
A flash EEPROM memory cell, comprising:
- a source region formed in a substrate and connected to a common line;
- a drain region formed in said substrate and connected to a bit line;
- a gate region located between said source region and said drain region;
- floating gate formed above said gate region and insulated from said gate region;
- a control gate formed above said floating gate and insulated from said floating gate, said control gate being connected to a word line;
- wherein during a reading operation, a negative voltage is applied to an unselected flash EEPROM memory cell on said word line.
Dependencies are inferred from the claim text.