Dynamic random access memory
OwnerSven E. Wahlstrominventor
Life of this patent
Estimating the term…
Abstract
A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.
Claims11
A dynamic random access memory comprising:
- a plurality of memory cells at the intersections of word lines and bit lines, said memory cells being coupled to a folded bit line, each memory cell comprising:
- a storage capacitor for storing charge representative of a stored value;
- a first, write transistor coupled to a first plate of said storage capacitor and a first bit line;
- and
- a second, read transistor having a first terminal thereof coupled to a first terminal of a third transistor and a second terminal coupled to a second bit line, said third transistor comprising a gate coupled to said first plate of said storage capacitor, said word line coupled with a gate of both said read transistor and said write transistor;
- and
- a sense amplifier coupled to said folded bit line.
A dynamic random access memory for integrated circuits, comprising a plurality of memory cells, each memory cell comprising:
- a storage capacitor in a first semiconductor layer;
- transistor elements in a second semiconductor layer, above said first semiconductor layer, wherein said first and second semiconductor layers are substantially parallel with a surface of a substrate wafer, and said capacitor is directly beneath said transistor elements;
- and
- said storage capacitor is coupled to said transistor elements.
A dynamic random access memory access comprising:
- a plurality of memory cells at the intersections of word lines and bit lines, said memory cells being coupled to a folded bit line, each memory cell comprising:
- a storage capacitor for storing charge representative of a stored value;
- a first, write transistor coupled to a first plate of said storage capacitor and a first bit line;
- and
- a second, read transistor having a first terminal thereof coupled to a first terminal of a third transistor and a second terminal coupled to a second bit line, said read transistor having a lower switching threshold than said write transistor, said third transistor comprising a gate coupled to said first plate of said storage capacitor, said word line coupled with a gate of both said read transistor and said write transistor;
- a fourth transistor coupled to said first bit line and ground, said fourth transistor permitting said first bit line to lose voltage at a reduced rate as compared to said second bit line when reading a high charge from said storage capacitor;
- a fifth transistor coupled to said first bit line and a clamp line having a clamp level, said clamp level being intermediate to ground and a switching threshold of said write transistor;
- and
- a sense amplifier coupled to said folded bit line.
Dependencies are inferred from the claim text.