Dynamic random access memory device with the combined open/folded bit-line pair arrangement

A semiconductor memory device comprising:

• a substrate;
• a plurality of word lines on said substrate;
• a plurality of bit lines transverse to said word lines on said substrate;
• an array of memory calls selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines, and said array of memory cells being divided into a plurality of subarray sections in the row direction along the bit lines;
• and
• a plurality of sense amplifiers each connected between adjacent two of said subarray sections and to said bit lines, adjacent two of said sense amplifiers operating, in a reading mode, in a folded bit-line scheme, and in a writing mode, in a folded bit-line scheme and an open bit-line scheme, respectively.

A semiconductor memory device comprising:

• a substrate;
• a plurality of word lines on said substrate;
• a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups having three bit lines;
• an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in a column direction along the word lines while said memory cells are arranged at all cross points along a center one of the three bit lines of each of said bit line groups, and said array of memory cells being divided into a plurality of subarray sections in a row direction of the bit lines;
• and
• a plurality of sense amplifiers each connected between adjacent two of said subarray sections, said sense amplifiers including a first sense amplifier connected to two of said bit lines of each of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged adjacent to said first sense amplifier and between adjacent two of said bit line groups and connected to a center one of the bit lines of each of the adjacent two bit line groups in an open bit-line scheme, said first sense amplifier being operated in a folded bit-line scheme while said second sense amplifier is operated in an open bit-line scheme.

A semiconductor memory device comprising:

• a substrate;
• a plurality of word lines on said substrate;
• a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups each having three bit lines;
• an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines and said array of memory cells being divided into a plurality of subarray sections in the row direction along the bit lines;
• and
• a plurality of sense amplifiers each connected between adjacent two of said bit line groups in the row direction along the bit lines, said sense amplifiers including a first sense amplifier connected to two of said three bit lines of each of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged neighboring to said first sense amplifier and connected between two of said bit line groups, which are adjacent to each other in the row direction of the bit lines, in an open bit-line scheme, thereto, in an open bit-line scheme;
• and
• a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said bit line groups which is adjacent to said second sense amplifier and two second switching circuits connected, respectively, between said second sense amplifier and said adjacent two bit line groups, said first switching circuit including three switching elements connected respectively to the three bit lines of one of said bit line groups and driven to connect said first sense amplifier to the bit lines of said one of said bit line groups in the folded bit-line scheme, and each of said second switching circuits including three switching elements connected to the three bit lines of one of said bit line groups and driven to connect the bit lines of said adjacent two bit line groups to said second sense amplifier in the open bit-line scheme.

A semiconductor memory device comprising;

• a substrate;
• a plurality of word lines on said substrate;
• a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups;
• an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, every two of said memory cells being arranged respectively at two of every adjacent three of the cross points in each of row and column directions along the bit lines and word lines, and said array of memory cells being divided into a plurality of subarray sections in the row direction along the bit lines;
• a plurality of sense amplifiers each connected between two of said bit line groups which are adjacent to each other in the row direction along the bit lines, said sense amplifiers including a first sense amplifier connected to two of said bit lines of one of said bit line groups in a folded bit-line scheme and a second sense amplifier arranged adjacent to said first sense amplifier in the column direction along said word lines and connected between said one of said bit line groups and the other which is neighboring thereto, in an open bit-line scheme;
• and
• a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said bit line groups which is arranged between said first and second sense amplifiers and two second switching circuits, one connected between said second sense amplifier and one of said adjacent two bit line groups and the other between said second sense amplifier and the other of said adjacent two bit line groups, said first switching circuit including switching elements connected respectively to the three bit lines of one of said bit line groups and driven to connect said first sense amplifier to the bit lines of said one of said bit line groups in the folded bit-line scheme, and each of said second switching circuits including three switching elements connected respectively to the three bit lines of one of said bit line groups and driven to connect the bit lines of said adjacent two bit line groups to said second sense amplifier in the open bit-line scheme.

A semiconductor memory device comprising:

• a substrate;
• a plurality of word lines on said substrate;
• a plurality of bit lines transverse to said word lines on said substrate, said bit lines being divided into a plurality of bit line groups in a direction along the bit lines and each of said bit line groups, said bit lines including a plurality of folded bit-line pairs and a plurality of bit-line pairs and each of the bit lines belonging to each of said open bit-line pairs being arranged to extend in a zig-zag manner between two bit lines of said folded bit-line pairs;
• an array of memory cells selectively arranged at a plurality of cross points defined between said word lines and said bit lines, said memory cells including a plurality of memory cells arranged along said folded-bit line pairs at every other cross point and a plurality of memory cells arranged at all cross points along said open bit-line pairs, and said array of memory cells being divided into a plurality of subarray sections in a row direction along the bit lines;
• a plurality of sense amplifiers each connected between two of said bit line groups which are adjacent to each other in the row direction along the bit lines, said sense amplifiers including a first sense amplifiers connected to said folded bit-line pairs of one of said bit line groups in a folded bit-line scheme and two second sense amplifiers arranged in the column direction along said word lines, each of said second sense amplifiers being connected between said one of said bit line groups and the other which is neighboring thereto, in an open bit-line scheme;
• and
• a plurality of switching sections including a first switching circuit connected between said first sense amplifier and one of said folded bit-line pairs and a second switching circuit connected between said second sense amplifier and one of said open bit-line pairs.