Back to results
US 5,396,448 AGranted
Associative memory system with hit entry detection circuit
AssigneeKabushiki Kaisha Toshiba
InventorsToshinari Takayanagi, Masanori Uchida
Life of this patent
Estimating the term…
Abstract
The associative memory capable of improving the efficiency in replacing an entry and testability of compare operation. The associative memory includes a Content Addressable Memory (CAM) cell array for executing a compare operation; a Random Access Memory (RAM) cell array for operating responsive to a result of the CAM cell array; and a HIT entry number detection circuit for receiving a result of the compare operation in the CAM cell array and outputting a HIT entry number.
Claims12
An associative memory system comprising:
- a content addressable memory (CAM) comprising rows in which entries of addresses are stored, said content addressable memory receiving an address and comparing the address with the addresses stored in said content addressable memory to provide a hit/miss signal on CAM match lines for indicating at least one matched entry, wherein there is a one-to-one correspondence between CAM match lines and the rows of said content addressable memory;
- a random access memory comprising rows in which data items are stored respectively corresponding to said entries of addresses, the rows of said random access memory being connected to the CAM match lines in a one-to-one correspondence;
- and
- an encoder comprising rows connected to said CAM match lines in parallel with said random access memory in a one-to-one correspondence for encoding said hit/miss signal indicating said at least one matched entry.
1 more element
An associative memory comprising:
- a content addressable memory for storing address data, said content addressable memory comprising n rows of content addressable memory cells, wherein each of said content addressable memory cells is coupled to a bit line for receiving a data bit input to said content addressable memory array, and wherein said content addressable memory outputs a hit/miss data word comprising n bits;
- a memory array comprising n rows in which data are stored, said memory array having n word lines to receive an n bit address word corresponding to said hit/miss data word, wherein said memory array is coupled in parallel to said content addressable memory;
- and
- an encoder connected to said n word lines to receive said n bit address word corresponding to said hit/miss data word, wherein said encoder generates an entry number identifying at least one row of said content addressable memory.
1 more element
Dependencies are inferred from the claim text.