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US 5,396,446 AGranted
Digital filter circuit that minimizes holding errors transmitted between holding circuits
AssigneeYozan Inc.
InventorsGuoliang Shou, Weikang Yang, Sunao Takatori, Makoto Yamamoto
Life of this patent
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Abstract
A filter circuit that controls holding errors so that such errors are held to a minimum. In the filter circuit, multipliers of multiplication circuits are stored in a shift register and multiplication is successively executed with various multipliers in a multiplication circuit by circulating multipliers in the shift register.
Claims6
A filter circuit for holding a plurality of successive analog input data in time series and for performing multiplication by multiplying said data by a multiplier in time series, comprising:
- i) a plurality of holding circuits for holding input data:
- ii) a plurality of multiplication circuits, wherein each multiplication circuit is associated with one of said holding circuits such that each multiplication circuit is connected to receive an output from said associated holding circuit;
- iii) a shift register having a plurality of data areas, wherein each data area corresponds to one of said multiplication circuits, data of each data area being input to each multiplication circuit as a multiplier therein, data in each data area being transferred to an adjacent data area, as well as being fed back to an initial data area when said data has been transferred to an ending data area in said shift register;
- and
- iv) an addition circuit for calculating a total summation of an output of each of said multiplication circuits.
2 more elements
Dependencies are inferred from the claim text.