Device for converting data from series to parallel

A device for converting data from series to parallel, comprising:

• a shift register means for delaying serial data by a number of bits of a synchronous signal pattern in accordance with a serial clock and outputting an output signal, the serial data being reproduced from a magnetic recording medium;
• a detector means for detecting a synchronous signal from the output signal received from said shift register means;
• a system controller for generating a predetermined bits interval of a parallel load signal and a parallel clock signal
• a parallel shift register means for converting the output signal received from said shift register means to a predetermined bits interval of parallel data in accordance with the parallel load signal received from said system controller;
• and
• counter part means for counting the parallel clock signal generated by said system controller to generate window signals detecting the synchronous signal in a certain period when said detector means detects the synchronous signal,
• wherein said system controller means generates the parallel load signal responsive to the synchronous signal received from said detector means and the window signals received from said counter part means.