A circuit for recording a program end signal for use in a video cassette tape recorder, comprises:
- a consecutive recording switch for outputting a signal selecting a consecutive recording mode for searching for an end portion of a program which has been previously recorded on a tape and consecutively recording a program;
- a program end recording means for outputting a control pulse to be recorded at a reference duty cycle which is generated from a servo system, modulating the control pulse at a predetermined duty cycle when a stop signal is inputted, delaying the stop signal and outputting a predetermined number of control pulses for indicating an end of program, and thereafter outputting said stop signal;
- and
- a program end detecting means for outputting a recording signal for operating the video cassette tape recorder in a recording mode when no control pulse is detected from the tape or after the program end indicating pulse is detected upon selection of the consecutive recording mode by the consecutive recording switch, wherein
- said program end detecting means includes
- an end indicating control pulse detecting means for receiving the signal from the consecutive recording switch as an enable signal and detecting a program end indicating control pulse modulated at a predetermined duty cycle among control pulses which are detected in a high speed advance travelling mode,
- a control pulse detecting means for receiving signal from the consecutive recording switch as an enable signal and detecting presence/absence of program end indicating control pulses which are detected in the high speed advance travelling mode, and
- a recording signal controller means for outputting a recording signal for operating the video cassette tape recorder in the recording mode when one of no program end indicating control pulse signal is detected at the control pulse detecting mean and a program end indicating control pulse is detected at the end indicating control pulse detecting means under the condition that one of the signals from the consecutive recording switch and a normal recording signal is inputted;
- and
- said end indicating control pulse detecting means includes
- a NAND-gate for NANDing the signal from the consecutive recording switch and a system clock signal,
- an N-bit counter for receiving an output signal from said AND-gate as a first clock signal and an inverted program end indicating control pulse detected from the tape through a control head as a reset signal and counting a high potential duty cycle of the inverted program end indicating control pulse,
- a septenary counter for receiving a predetermined count value of which the duty cycle of the inverted program end indicating control pulse is counted as a second clock signal and counting the number of second clock signals until being reset by the recording signal from the recording recording signal/controller means, and
- a latch for latching and outputting count signals of the septenary counter which are over the predetermined value until said stop signal is outputted from the program end recording means.