Low signal margin detect circuit

A system for testing a plurality of logic circuits comprising:

• a plurality of testing circuits each of which is connected to at least one logic output signal of said plurality of logic circuits;
• each of said testing circuits including:
• means for activating said testing circuit in response to an activation signal;
• means for receiving and amplifying a first input signal and a second input signal;
• said amplifying means comprising:
• means for conductively receiving a first voltage potential;
• a first and second transistor each having a base, collector and emitter;
• said collectors of said first and second transistors being connected via respective resistors to said first voltage potential;
• said emitters of said first and second transistors being connected to said activating means;
• and
• said first and second input signals being respectively applied to the base of said first and second transistors;
• means for detecting a difference between said first and second amplified signals;
• said detecting means comprising:
• third and fourth transistors each having a base, emitter and collector;
• a third resistor connected to a first connection node between said means for receiving said first voltage potential and said collectors of said third and fourth transistors;
• said base of said third transistor and said emitter of said fourth transistor being commonly connected to a second connection node between said collector of said first transistor and said first resistor;
• said base of said fourth transistor and said emitter of said third transistor being commonly connected to a third connection node between said collector of said second transistor and said second transistor;
• means responsive to said detecting means for generating a difference signal at said first connection node;
• means responsive to said difference signal for signalling a first and second error signal when said detected difference is below a given signal difference threshold;
• means for combining said first error signal from each of said plurality of testing circuits in a first direction;
• means for combining said second error signal from each of said plurality of testing circuits in a second direction orthogonal to said first direction;
• and
• means for testing said combined signals in said first and second directions to identify said logic circuit with said error.