Single chip IC tester architecture

A method for performing a functional test of integrated circuits at speed using a tester apparatus which includes a test bus having control and data signal lines, a test bus controller for transmitting stimulus data to and receiving response data from a device under test (DUT), and a boundary-scan architecture which includes a plurality of registers coupled to the test bus including an instruction register for receiving clock and control signals from the test bus controller and storing the clock and control signals as large instruction sets, a boundary-scan register including a plurality of input and output boundary-scan cells for buffering stimulus and response signals associated with the DUT, a bypass register for providing a signal path by which test data can be routed without interference with a subsequent serially connected DUT, and a test data register for storing test parameters associated with the DUT, said method comprising the steps of:

• a) generating a high frequency clock signal as stimuli is applied to the DUT;
• b) dividing said high frequency clock signal into a desired test rate frequency in response to test rate information received from the test data register;
• and
• c) determining a number of test cycles for the DUT from divided clock signal information and test cycle count data received from the test data register.