Output circuit for interfacing integrated circuits having different power supply potentials

A first integrated circuit having an first output driver which is to interface with a second output driver located within a second integrated circuit, the first output driver being powered by a first voltage and the second output driver being powered by a second voltage wherein the first voltage is less than the second voltage, the first output driver comprising:

• a power supply voltage conductor for providing the first voltage;
• a data input conductor for providing a data input signal;
• an output enable conductor for providing an output enable signal;
• a well conductor used to bias at least one diffusion well containing at least one transistor within the first output driver;
• means for generating a control signal containing at least one transistor and having a first terminal coupled to the power supply voltage conductor, a second terminal coupled to the output enable conductor, a third terminal coupled to the well conductor, and a fourth terminal coupled to the data input conductor, the means for generating driving a control signal conductor to the first voltage response to the deactivation of the control signal, the means for generating discharging the control signal and a gate voltage on the at least one transistor at a substantially equal rate to reduce gate oxide stress;
• and
• means for providing an output logic value onto a output conductor, the means for providing having a first terminal coupled to the output conductor, a second terminal for receiving the first voltage through at least one pull-up transistor, a third terminal coupled to the well conductor, and a fourth terminal coupled to the control signal conductor, the means for providing discharging a voltage on the well conductor from the second voltage in a manner which tracks the voltage of the control signal conductor to reduce electric field stress across a gate oxide of the pull-up transistor.

An output circuit comprising:

• a first transistor having a control electrode for receiving a control signal, a first current electrode for receiving a supply voltage, a channel region coupled to a channel conductor which is used to bias the channel region, and a second current electrode electrically coupled to the channel conductor;
• a second transistor having a control electrode for receiving the supply voltage, a first current electrode coupled to the channel conductor, a channel region coupled to the channel conductor, and a second current electrode electrically coupled to the control signal;
• a third transistor having a control electrode for receiving the control signal, a first current electrode for receiving the supply voltage, a channel region coupled to the channel conductor, and a second current electrode electrically coupled to an output;
• and
• a fourth transistor having a control electrode for receiving the supply voltage, a first current electrode coupled to the channel conductor, a channel region coupled to the channel conductor, and a second current electrode electrically coupled to the output.

A circuit for providing a control signal within an output buffer, the circuit comprising:

• a first n-channel transistor having a first current electrode for receiving a power supply voltage, a second current electrode, and a control electrode coupled to an inverted output enable;
• a second n-channel transistor having a first current electrode coupled to the second current electrode of the first n-channel transistor, a second current electrode, and a control electrode for receiving the power supply voltage;
• a third n-channel transistor having a first current electrode coupled to the second current electrode of the second n-channel transistor, a second current electrode, and a control electrode for receiving the power supply voltage;
• a fourth n-channel transistor having a first current electrode coupled to the second current electrode of the third n-channel transistor, a second current electrode for receiving a ground potential, and a control electrode coupled to an output enable;
• and
• a first p-channel transistor having a channel region formed in an n-well wherein the n-well is connected to a conductor which affects the bias of the channel region, a first current electrode coupled to the channel region, a second current electrode coupled to the second current electrode of the second n-channel transistor, and a control electrode for receiving the power supply voltage.

An output buffer circuit comprising:

• a first n-channel transistor having a first current electrode for receiving a power supply voltage, a second current electrode, and a control electrode coupled to an output enable;
• a second n-channel transistor having a first current electrode coupled to the second current electrode of the first n-channel transistor, a second current electrode, and a control electrode for receiving the power supply voltage;
• a third n-channel transistor having a first current electrode coupled to the second current electrode of the second n-channel transistor, a second current electrode, and a control electrode for receiving the power supply voltage;
• a fourth n-channel transistor having a first current electrode coupled to the second current electrode of the third n-channel transistor, a second current electrode for receiving a ground potential, and a control electrode coupled to the output enable;
• a first p-channel transistor having a channel region formed in an n-well wherein the n-well is connected to a conductor which affects the bias of the channel region, a first current electrode coupled to the channel region, a second current electrode coupled to the second current electrode of the second n-channel transistor, and a control electrode for receiving the power supply voltage;
• a second p-channel transistor having a first current electrode for receiving the power supply voltage, a second current electrode, and a control electrode coupled to the output enable;
• a third p-channel transistor having a first current electrode coupled to the second current electrode of the second p-channel transistor, a second current electrode, and a control electrode coupled the second current electrode of the first p-channel transistor;
• a fifth n-channel transistor having a first current electrode coupled to the second current electrode of the third p-channel transistor, a second current electrode coupled to the ground potential, and a control electrode coupled to the output enable;
• a fourth p-channel transistor having a control electrode coupled to the second current electrode of the third p-channel transistor, a first current electrode for receiving a supply voltage, a channel region coupled to the conductor which affects the bias of the channel region, and a second current electrode electrically coupled to the conductor which affects the bias of the channel region;
• a fifth p-channel transistor having a control electrode for receiving the power supply voltage, a first current electrode coupled to the conductor which affects the bias of the channel region, a channel region coupled to the conductor which affects the bias of the channel region, and a second current electrode electrically coupled to the second current electrode of the third p-channel transistor;
• a sixth p-channel transistor having a control electrode coupled to the second current electrode of the third p-channel transistor, a first current electrode for receiving the power supply voltage, a channel region coupled to the conductor which affects the bias of the channel region, and a second current electrode electrically coupled to the conductor which affects the bias of the channel region;
• and
• a seventh p-channel transistor having a control electrode for receiving the power supply voltage, a first current electrode coupled to the conductor which affects the bias of the channel region, a channel region coupled to the conductor which affects the bias of the channel region, and a second current electrode electrically coupled to the output.

An output buffer circuit comprising:

• an output;
• a drive-hi control signal for substantially driving the output to a logic high value;
• a plurality of p-channel transistors wherein a first p-channel transistor is coupled to a second p-channel transistor, the second p-channel transistor is coupled to a third p-channel transistor, and the third p-channel transistor is coupled to a fourth p-channel transistor, the plurality of p-channel transistors being coupled for selectively providing the logic high value to the output in response to the drive-hi control signal, the first p-channel transistor being coupled to a supply voltage, the second p-channel transistor being connected in series directly between the well conductor and the drive-hi signal the plurality of p-channel transistors being capable of receiving a voltage greater than the supply voltage from the output without adverse leakage current resulting from the output to the supply voltage, the plurality of p-channel transistors having a gate to channel voltage which does not exceed 4.1 volts;
• and
• circuitry, coupled to the output, for selectively providing a logic low value to the output.

An output driver comprising:

• a p-channel pull-up transistor having a first current electrode connected to a power supply voltage, a second current electrode coupled to a data output line, a n-well conductor which allows the voltage of a channel region of the pull-up transistor to be altered, and a control electrode for receiving a first control signal;
• an n-channel pull-down transistor having a first current electrode connected to a ground potential, a second current electrode coupled to the data output line, and a control electrode for receiving a second control signal;
• and
• a single p-channel transistor having a first current electrode coupled to the n-well conductor, a second current electrode coupled to the first control signal, a channel region coupled to the n-well conductor, and a control electrode for receiving the power supply voltage, the single p-channel transistor selectively coupling the n-well conductor to the first control signal.

A method for driving a data value onto a conductor, the method comprising the steps of:

• having the conductor at a first voltage;
• determining that the data value is to be driven onto the conductor;
• lowering the voltage of the conductor from the first voltage to a second voltage wherein the second voltage is less than the first voltage, the lowering being performed in response to a control signal and being performed before the data value is driven on the conductor;
• and
• driving the data value onto the conductor.

A system for providing a data value through a conductor, the system having an output enable control signal and comprising:

• a first transistor for providing a first power supply voltage to the conductor;
• a second transistor for providing a second power supply voltage to the conductor wherein the second voltage is different from the first voltage;
• and
• a precondition control signal coupled to the first transistor for driving the conductor from a third voltage to the second voltage wherein the second voltage is less than the third voltage, the third voltage being driven to the second voltage in preparation for the assertion of the output enable control signal.