FPGA with distributed switch matrix

An integrated circuit that implements a programmable logic function, and comprising:

• an array of programmable function units;
• a group of first routing conductors aligned parallel to a first axis of said array;
• and
• a group of second routing conductors aligned parallel to a second axis that is different from said first axis;
• Characterized in that said integrated circuit further comprises a group of third routing conductors, and wherein each of said third routing conductors includes at least two programmable interconnect means for programmably connecting selected ones of said first routing conductors to selected ones of said second routing conductors.

An integrated circuit comprising at least two adjacent programmable logic cells each comprising:

• a programmable function unit,
• a group of access routing conductors connected to inputs and outputs of the programmable function unit;
• and
• a group of inter-block routing conductors;
• Characterized in that said adjacent programmable logic cells each further comprise a group of switching routing conductors, wherein each of said switching routing conductors includes at least two programmable interconnect means, that programmably connect said group of access routing conductors and said group of inter-block routing conductors;
• and further characterized in that group of switching routing conductors in one of said adjacent programmable logic cells also programmably connect to at least one group of switching routing conductors in another of said adjacent programmable logic cells.