Circuit redundancy having a variable impedance circuit

A semiconductor integrated circuit having a function of storing information, comprising:

• first and second data lines for reading out information;
• a first normal cell group and a first spare cell group commonly connected to said first data line such that information is read out onto said first data line;
• a second normal cell group and a second spare cell group commonly connected to said second data line such that information is read out onto said second data line;
• selecting amplifier means for selecting and amplifying either one of information on said first data line and information on said second data line;
• decoding means for supplying, according to an input address, either one of (i) a first block selecting signal for selecting said first normal cell group, and (ii) a second block selecting signal for selecting said second normal cell group, said decoding means being adapted to supply a normal global selecting signal for selecting one cell of said first normal cell group, or one cell of said second normal cell group;
• first switch means for controlling, based on said first or second block selecting signal and said normal global selecting signal supplied from said decoding means, such that information is read out onto said first data line from one cell of said first normal cell group when said first normal cell group is selected by said first block selecting signal, and that information is read out onto said second data line from one cell of said second normal cell group when said second normal cell group is selected by said second block selecting signal;
• redundancy judging means for making a judgment of whether or not a plurality of stored spare addresses contain an address identical with said input address, said redundancy judging means being adapted to supply, according to said input address, a spare global selecting signal for selecting one cell of said first spare cell group or one cell of said second spare cell group only when said plurality of spare addresses contain said spare address identical with said input address, said redundancy judging means being adapted to designate, based on the result of said judgment, which information is to be amplified by said selecting amplifier means, out of information on said first data line and information on said second data line;
• and
• second switch means for controlling, based on said first or second block selecting signal supplied from said decoding means and said spare global selecting signal supplied from said redundancy judging means, such that information is read out onto said second data line from one cell of said second spare cell group when said first normal cell group is selected by said first block selecting signal, and that information is read out onto said first data line from one cell of said first spare cell group when said second normal cell group is selected by said second block selecting signal;
• whereby said redundancy judging means is adapted such that, in the case said plurality of spare addresses do not contain said address identical with said input address, (i) said selecting amplifier means amplifies information on said first data line when said first normal cell group is selected by said first block selecting signal, and (ii) said selecting amplifier means amplifies information on said second data line when said second normal cell group is selected by said second block selecting signal, and said redundancy judging means is adapted such that, in the case said plurality of spare addresses contain said address identical with said input address, (i) said selecting amplifier means amplifies information on said second data line when said first normal cell group is selected by said first block selecting signal, and (ii) said selecting amplifier means amplifies information on said first data line when said second normal cell group is selected by said second block selecting signal.