Offset detecting circuit and output circuit and integrated circuit including the output circuit

An output circuit, comprising:

• an offset detecting circuit, comprising:
• a reference voltage input terminal for receiving a reference voltage;
• a first sample and hold circuit for holding said reference voltage received by said reference voltage input terminal;
• a first buffer amplifier having a first pair of input terminals including a first non-inversion input terminal and a first inversion input terminal and a second pair of input terminals including a second non-inversion input terminal and a second inversion input terminal, said reference voltage terminal being connected to at least one of said first pair of input terminals, and an output signal of said first sample and hold circuit being applied to said second non-inversion input terminal of said second pair of input terminals;
• and
• a signal voltage outputting circuit, comprising:
• a second sample and hold circuit for holding a signal voltage inputted thereto;
• a second buffer amplifier having a third pair of input terminals including a third non-inversion input terminal and a third inversion input terminal and a fourth pair of input terminals including a fourth non-inversion input terminal and a fourth inversion input terminal, said third non-inversion input terminal being connected to said reference voltage input terminal, said third inversion terminal being connected to said second inversion terminal, output signal of said second sample and hold circuit being applied to said fourth non-inversion input terminal and an output signal of said second buffer amplifier being applied to said fourth inversion input terminal and to a signal output terminal, wherein said second buffer amplifier outputs a signal whereby a total offset of said second sample and hold circuit and of said second buffer amplifier are canceled.

A semiconductor integrated circuit, comprising:

• an offset detecting circuit, comprising:
• a reference voltage input terminal for receiving a reference voltage;
• a first sample and hold circuit for holding said reference voltage received by said reference voltage input terminal;
• a first buffer amplifier having a first pair of input terminals including a first non-inversion input terminal and a first inversion input terminal and a second pair of input terminals including a second non-inversion input terminal and a second inversion input terminal, said reference voltage terminal being connected to at least one of said first pair of input terminals, and an output signal of said first sample and hold circuit being applied to said second non-inversion input terminal of said second pair of input terminals;
• and
• a signal voltage outputting circuit, comprising:
• a second sample and hold circuit for holding a signal voltage inputted thereto;
• a second buffer amplifier having a third pair of input terminals including a third non-inversion input terminal and a third inversion input terminal and a fourth pair of input terminals including a fourth non-inversion input terminal and a fourth inversion input terminal, said third non-inversion input terminal being connected to said reference voltage input terminal, said third inversion terminal being connected to said second inversion input terminal, and an output signal of said second sample and hold circuit being applied to said fourth non-inversion input terminal and an output signal of said second buffer amplifier being applied to said fourth inversion input terminal and to a signal output terminal, wherein said second buffer amplifier outputs a signal whereby a total offset of said second sample and hold circuit and of said second buffer amplifier are canceled.