US 5,396,111 A · Clocking unit for digital data processing

Abstract

A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such that the latter signals are substantially synchronous with the processor clock signals. D-flip-flop circuitry together with a delay unit having an adjustable time delay are used to generate a gated clock signal. The overall time delay, from the time of which the circuitry is enabled until the gated clock signal is produced, is appropriately set by selecting the required time delay so that the overall time delay is essentially the same as the time delay required to generate the processor clock signals. Accordingly, the edges of the gated clock signals can be made to coincide with the edges of the processor clock signals. The use of such gated clock signal generation circuitry can reduce the time needed to generate the gated clock signals from that required by previously used register PAL circuitry to improve performance of the processing system.

Claims9

Dependent claims

A clock generator system for generating at least one gated clock signal for use in a data processing system which includes a processor and at least one unit for providing an output signal from an input signal when enabled by said gated clock signal, said clock generator system comprising

a reference clock generator connected to said processor for providing an internal reference clock signal in response to a free-running clock signal in said processor;
a processor clock generator connected to said reference clock generator and responsive to said internal reference clock signal for providing at least one processor clock signal;
a gated clock generator connected to said reference clock generator and responsive to said internal reference clock signal and connected to said processor and responsive to an enable signal therefrom for producing at least one gated clock signal;
and
time delay circuitry connected to said gated clock generator for providing a time delay for said gated clock signal to provide a time delayed gated clock signal which is substantially synchronous with said at least one processor clock signal.

2 more elements

A clock generator system for generating a plurality of gated clock signals for use in a data processing system which includes a processor and a plurality of operating units each for providing an output signal from an input signal when enabled by one of said gated clock signals, said clock generator system comprising

a reference clock generator connected to said processor for providing an internal reference clock signal in response to a free-running clock signal in said processor;
a processor clock generator connected to said reference clock generator and responsive to said internal reference clock signal for providing a plurality of processor clock signals which are in phase with each other;
a gated clock generator connected to said reference clock generator and responsive to said internal reference clock signal and connected to said processor and responsive to a plurality of enable signals therefrom for producing a plurality of gated clock signals;
and time delay circuitry connected to said gated clock generator for providing a time delay for each of the plurality of gated clock signals produced thereby to provide a plurality of time delayed gated clock signals each of which is synchronous with said processor clock signals.

1 more element

Dependencies are inferred from the claim text.

Clocking unit for digital data processing

Life of this patent

Clocking unit for digital data processing

Life of this patent

Abstract

Claims9