Bit clock regenerating circuit and data regenerating method
AssigneeOlympus Optical Co., Ltd.
InventorMitsuo Oshiba
Life of this patent
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Abstract
A bit clock regenerating circuit comprising an edge detector made up of two flip-flops for detecting edges of a binary signal and a gating circuit, a counter receiving an edge detected pulse from the edge detector as a load signal for setting an initial value, counting clock pulses with a given frequency, and generating a bit clock according to the result of the counting, and a ROM in which multiple conversion tables are formed to supply an initial value for the counter according to an output value of the counter, and a conversion table for determining regeneration conditions is selected according to a switching signal.
Claims4
A bit clock regenerating circuit comprising:
- an edge detecting means for producing an edge detection pulse upon detection of an edge of a binary input signal;
- a counting means in which an initial value is set in accordance with said edge detection pulse serving as a load signal and which counts clock pulses of a given frequency;
- a plurality of conversion tables associated with reference cycles of said binary input signal, said plurality of conversion tables having initial values to be supplied to said counting means, said initial value being determined in accordance with an output value of said counting means;
- and
- a conversion table selecting means including a reference cycle calculating means for calculating a reference cycle of pulse spacings using pulse spacings of said binary signal, said conversion table selecting means selecting a conversion table from among said plurality of conversion tables associated with reference cycles according to an output value of said reference cycle calculating means, and generating a bit clock according to an output value of said reference cycle calculating means and an output value of said counting means.
Dependencies are inferred from the claim text.