Circuit for high resolution decoding of multi-anode microchannel array detectors

A circuit for high resolution decoding of multi-anode microchannel array detectors comprising:

• a plurality of input registers accepting transient inputs from an anode array;
• anode encoding logic means connected to said plurality of input registers for converting k-fold anode array events into an equivalent two-fold event for an arbitrary k;
• a plurality of midpoint pipeline registers connected to said anode encoding logic means for storing said equivalent two-fold events and for storing information pertaining to the number of anodes illuminated in said anode array;
• pixel decoding logic means connected to said midpoint pipeline registers for converting said equivalent two-fold events into a corresponding standard ten bit pixel address location;
• high resolution algorithm circuit means having a user selectable even-odd discrimination mode and operating in parallel with said pixel decoding logic means for generating a high resolution least significant bit to enhance said multi-anode microchannel array detector's spatial resolution by halving the pixel size and doubling the number of pixels in each axis of said anode array;
• multiplexer means connected to said pixel decoding logic means for allowing a user selectable pixel address output according to the actual multi-anode microchannel array detector anode array size;
• an output register for concatenating said high resolution least significant bit onto said standard ten bit pixel address location thereby providing a full eleven bit pixel address, and for storing said full eleven bit pixel address;
• and
• timing and control state means connected to said plurality of input registers, said anode encoding logic means, and said output register for managing the overall operation of said circuit for high resolution decoding of multi-anode microchannel array detectors.