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US 5,395,799 AGranted
Method of fabricating semiconductor devices having electrodes comprising layers of doped tungsten disilicide
AssigneeAT&T Corp.
InventorChen-Hua D. Yu
Life of this patent
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AssigneeAT&T Corp.
InventorChen-Hua D. Yu
Estimating the term…
A workpiece is formed comprising a silicon substrate covered by four successive layers of silicon dioxide, undoped polysilicon, undoped WSi.sub.2 and a top layer of silicon dioxide on silicon nitride. The four layers are patterned to provide gate electrode structures each comprising the four layers. The workpiece is covered with a masking layer and the top layer of each structure is exposed through the masking layer. The top layers are then removed and ions of one conductivity type are implanted into the WSi.sub.2 layers of one group of gate electrode structures while another group of structures is masked, and ions of the other conductivity type are implanted into the WSi.sub.2 layers of the second group while the first group is masked. Thereafter, doped regions are formed in the substrate adjacent to the gate electrode structures.
A method of fabricating a semiconductor device comprising the steps of forming, on a surface of a semiconductor substrate and in the named order, a first layer of a dielectric material, a second layer of undoped silicon, and a third layer of undoped tungsten disilicide, selectively patterning all said three layers to provide spaced apart first and second structures, each structure comprising said three layers, and each structure adjoining exposed surface portions of said substrate, doping said third layer of said first structure with P type ions while said third layer of said second structure is masked against said P type doping, doping said third layer of said second structure with N type ions while said third layer of said first structure is masked against said N type doping, and wherein, said doping with P type ions is performed by coating said first and second structures and said adjoining exposed surface portions with a first masking layer, selectively patterning said first masking layer for exposing said third layer of both said structures, covering both said structures, said exposed third layer of said structures and said adjoining exposed surface portions of said substrate with a second masking layer, selectively patterning said second masking layer for exposing said third layer of said first structure while leaving said third layer of said second structure and said adjoining surface portions masked by said second masking layer, and ion implanting said P type ions into said exposed third layer of said first structure.
A method of fabricating a semiconductor device comprising forming, on a surface of a semiconductor substrate, first and second spaced apart structures each comprising, in the named order, a first layer of a dielectric material on the substrate surface, a second layer of undoped polysilicon, a third layer of undoped tungsten disilicide, and a fourth layer of a material selectively etchable with respect to said third layer, covering said structures and portions of said substrate surface adjacent to said structures with a first masking layer, providing first openings through said first masking layer for selectively exposing the upper surfaces of said fourth layers of both said structures, selectively removing, through said openings, said fourth layers thereby exposing the upper surfaces of said third layers of tungsten disilicide, covering said first masking layer, including said exposed upper surfaces of said third layers of tungsten disilicide, with a second masking layer, providing a second opening through said second masking layer for exposing said third layer of said first structure while said third layer of said second structure is covered by said second masking layer, and, in a first ion implantation step, implanting ions into said third layer of said first structure.
Dependencies are inferred from the claim text.