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US 5,395,790 AGranted
Stress-free isolation layer
AssigneeUnited Microelectronics Corp.
InventorWater Lur
Life of this patent
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Abstract
A method of fabricating a stress-free isolation layer for semiconductor integrated circuit that solves the problems of crystalline defects and the degraded characteristics of devices due to the presence of structural stresses. Partial trench etching is employed to form at least one narrow trenches, followed by anneal-treating to release stress and eliminate crystalline defects therein. Isolating material is then filled into the narrow trenches to form a complete stress-free isolation layer.
Claims12
A method of fabricating a stress-free isolation layer for semiconductor integrated circuits comprising the steps of:
- (a) providing a silicon substrate;
- (b) forming, sequentially, a) a pad oxide layer, b) a polysilicon layer, and c) a silicon nitride layer on said silicon substrate;
- (c) etching said silicon nitride layer, said polysilicon layer, and said pad oxide layer to expose predetermined areas of said silicon substrate;
- (d) etching said pre-determined areas of said silicon substrate to form at least one shallow trench;
- (e) forming sidewall spacer nitride layers on side walls of said shallow trench in said silicon substrate;
- (f) forming a field oxide layer that fills said shallow trench;
- (g) etching designated areas of said field oxide layer to form at least one narrow trench in said field oxide layer;
- (h) selectively ion implanting impurities through said at least one narrow trench into said silicon substrate;
- (i) annealing said silicon substrate to release system stress, and to form a channel-stop layer in said silicon substrate;
- (j) depositing an insulating layer to fill said at least one narrow trench in said field oxide layer to form the isolation layer;
- and
- (k) stripping said silicon nitride layer, said polysilicon layer, and said pad oxide layer.
9 more elements
Dependencies are inferred from the claim text.