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US 5,395,776 AGranted
Method of making a rugged DMOS device
AssigneeAT&T Corp.
InventorMuhammed A. Shibib
Life of this patent
Estimating the term…
Abstract
A method of making a doubly-diffused MOS (DMOS) device that can tolerate higher drain dV/dt before latch-up occurs. At least some of the immediately adjacent multiple body regions in the DMOS device are interconnected at the corners thereof by the formation of P-conductivity regions. These regions reduce parasitic bipolar effects and facilitate collection of excess carriers in the device that causes latch-up under high dV/dt conditions and reduced avalanche energy tolerance.
Claims9
A method of making an MOS controlled transistor having:
- a substrate of a first conductivity type with a major surface;
- a plurality of laterally displaced, spaced apart, first regions of a second conductivity type extending from the major surface of the substrate to a first depth;
- a second region of the first conductivity type within each of the first regions and extending from the major surface of the substrate to a depth less than the first depth;
- CHARACTERIZED BY THE STEP OF:
- forming third regions of the second conductivity type in the substrate and in contact with the first regions, for interconnecting immediately adjacent first regions.
2 more elements
A method of making an MOS controlled transistor having:
- a substrate of a first conductivity type with a major surface;
- CHARACTERIZED BY THE STEPS OF:
- forming a plurality of laterally displaced, spaced apart, first regions of a second conductivity type extending from the major surface of the substrate to a first depth;
- forming a second region of the first conductivity type within each of the first regions and extending from the major surface of the substrate to a depth less than the first depth;
- and
- forming third regions of the second conductivity type in the substrate and in contact with the first regions, for interconnecting immediately adjacent first regions;
- and
- depositing metal conductors to contact the first and second regions;
- wherein the third regions have a resistivity less than the substrate resistivity, the first regions are disposed in rows and columns, and the conductors interconnect the first and second regions to form a first terminal of the transistor.
6 more elements
Dependencies are inferred from the claim text.