Read only memory for storing multi-data

A memory cell for storing multi-data of different addresses, comprising:

• a transistor element having a control electrode for receiving a row selection signal, a first conduction terminal having one of either of two states,
• i. an open state, and
• ii. receiving a reference potential;
• and
• a second conduction terminal for transmitting stored data to an internal data transmission line;
• said reference potential being selectively established in response to an externally applied potential designating signal to a first level in a first access cycle for accessing said memory cell and to a second level in a second access cycle for accessing said memory cell.

A storage element for storing multi-data of different addresses comprising:

• a first transistor element having a control electrode coupled to receive a first row select signal, a first conduction terminal coupled to a common node and a second conduction terminal coupled to a first internal data transmission line;
• and
• a second transistor element having a control electrode coupled to receive a second row select signal generated independently of said first row select signal, a first conduction terminal coupled to the common node, and a second conduction terminal coupled to a second internal data transmission line;
• said common node coupled to one of at least three reference potential transmitting lines to receive a reference potential thereon selectively established in response to an applied potential designating signal.

A semiconductor read only memory device comprising:

• a plurality of word lines and a plurality of bit lines arranged in a plurality of rows and columns;
• at least three voltage reference lines;
• a plurality of memory cells arranged in a matrix, each memory cell being able to store multi-data of different addresses and comprising at least one transistor having a control electrode connected to a respective one of said word lines, a first conduction terminal directly connected to a respective one of said bit lines, and a second conduction terminal being connected in one of either the two following manners,
• i. directly connected to one of said voltage reference lines, and
• ii. disconnected from all of said voltage reference lines;
• and
• means for selectively establishing the voltage level of at least one of said at least three voltage reference lines.

In a storage element including a transistor element having a first conduction terminal at one, but not both, of either of two states,

• i. an open state, and
• ii. a state of receiving a reference potential, said storage element storing multi-data of different addresses,
• a method of reading data comprising the steps of:
• selectively establishing a potential at said first conduction terminal according to an externally applied potential designating signal in any access cycle for access to said storage element;
• and
• according to an applied address, rendering said transistor element conductive to form a current flow path between said first conduction terminal and an internal data transmission line.