Radar processing apparatus and method
AssigneeMassachusetts Institute of Technology
InventorsJames V. Pieronek, Jeffrey L. Gertz
Life of this patent
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Abstract
A radar processor comprises a multi-port memory device having memory which can be accessed by at least three ports. A first port receives input data from a data providing means. A second port couples a first processor which performs radar processing. A third port couples at least one second processor which assists the first processor by also performing radar processing. The multi-port memory device further includes an arbiter for coordinating and determining when each of the three ports can access the memory of the multi-port memory device. The first and second processors share information with each other via the multi-port memory device.
Claims6
A radar processor, comprising:
- a first multi-port memory device having memory which can be accessed by at least three ports, the device including
- a first port for receiving input radar data from a data providing means,
- a second port coupled to the input of an array signal processor which performs radar processing,
- a third port coupled to a first digital signal processor which performs radar processing, and
- an arbiter for coordinating and determining when each of the three ports can access the memory of the first multi-port memory device,
- wherein the array signal processor and the first digital signal processor communicating with each other via the first multi-port memory device,
- a second multi-port memory device having memory which can be accessed by at least three ports, the device including
- a first port coupled to the output of the array signal processor,
- a second port coupled to the input of a message interface processor which formats radar target and weather reports from processed radar data,
- a third port coupled to a second digital signal processor which performs radar processing, and
- an arbiter for coordinating and determining when each of the three ports can access the memory of the second multi-port memory device,
- wherein the array signal processor and the second digital signal processor communicate with each other via the second multi-port memory device, and the first and second digital signal processors communicate with each other via a separate interface between the first and second digital signal processors.
Dependencies are inferred from the claim text.