Back to results
US 5,394,114 AGranted
One nanosecond resolution programmable waveform generator
AssigneeNational Semiconductor Corporation
InventorCraig M. Davis
Life of this patent
Estimating the term…
Abstract
Generation of clock waveforms which have a frequency, phase offset, and duty cycle that is relative to a periodic reference signal. The outputs of a voltage controlled ring oscillator are directly applied to drive the inputs of a programmable AND, fixed OR array (PAL) to produce pulses of varied and phase offset and duty cycle. The phase offset has a resolution of one nanosecond. Additionally, the pulses generated can be ORed together within the PAL to produce clock waveforms that are multiples of the input frequency.
Claims46
A circuit for generating a high-resolution periodic waveform, comprising:
- oscillator means for generating a plurality of delayed oscillator signals in response to an error signal;
- a plurality of ANDing means for generating a plurality of clock signals so that each ANDing means generates one clock signal, each ANDing means comprising:
- receiving means for receiving the plurality of delayed oscillator signals, and
- generating means for generating a clock signal from the delayed oscillator signals received by the receiving means by passing a single delayed oscillator signal, and by performing a logical AND operation on two or more delayed oscillator signals;
- a plurality of driver means for generating a plurality of clock driver output signals so that each driver means generates one clock driver output signal, each driver means comprising:
- means for receiving one clock signal, and
- means for generating a clock driver output signal in response to said one clock signal;
- feedback means for feeding back one of the clock driver output signals as a feedback signal;
- and
- comparison means for generating the error signal by comparing the feedback signal and a reference signal.
7 more elements
A circuit for generating a high-resolution periodic waveform, comprising:
- oscillator means for generating a plurality of delayed oscillator signals in response to an error signal;
- a plurality of ANDing means for generating a plurality of intermediate clock signals so that each ANDing means generates one intermediate clock signal, each ANDing means comprising:
- first receiving means for receiving the delayed oscillator signals, and
- first generating means for generating an intermediate clock signal from the delayed oscillator signals received by the first receiving means by passing a single delayed oscillator signal, and by performing a logical AND operation on two or more delayed oscillator signals;
- a plurality of ORing means for generating a plurality of output clock signals so that each ORing means generates one output clock signal, each ORing means comprising:
- second receiving means for receiving one or more intermediate clock signals;
- and
- second generating means for generating an output clock signal from the one or more intermediate clock signals received by the second receiving means by passing a single intermediate clock signal, and by performing a logical OR operation on two or more intermediate clock signals;
- a plurality of driver means for generating a plurality of clock driver output signals so that each driver means generates one clock driver output signal, each driver means comprising:
- means for receiving one output clock signal, and
- means for generating a clock driver output signal in response to said one output clock signal;
- feedback means for feeding back one of the clock driver output signals as feedback signal;
- and
- comparison means for generating the error signal by comparing the feedback signal and a reference signal.
11 more elements
A method for generating a high-resolution periodic waveform, the method comprising the steps of:
- generating a plurality of delayed oscillator signals in response to an error signal;
- generating a plurality of clock signals, each clock signal being generated by passing a single delayed oscillator signal, and by performing a logical AND operation on two or more delayed oscillator signals;
- generating a clock driver output signal in response to each clock signal;
- feeding back one of the clock driver output signals as a feedback signal;
- and
- generating the error signal by comparing the feedback signal and a reference signal.
3 more elements
A method for generating a high-resolution periodic waveform, the method comprising the steps of:
- generating a plurality of delayed oscillator signals in response to an error signal;
- generating a plurality of intermediate clock signals, each intermediate clock signal being generated by passing a single delayed oscillator signal, and by performing a logical AND operation on two or more delayed oscillator signals;
- generating one or more output clock signals, each output clock signal being generated by passing a single intermediate clock signal, and by performing a logical OR operation on two or more intermediate clock signals;
- generating a clock driver output signal in response to each output clock signal;
- feeding back one of the clock driver output signals as a feedback signal;
- and
- generating the error signal by comparing the feedback signal and a reference signal.
4 more elements
A circuit for generating a high-resolution periodic waveform, the circuit comprising:
- an oscillator that generates a plurality of delayed oscillator signals in response to an error signal;
- a logic array that receives the delayed oscillator signals, that forms a plurality of sets of delayed oscillator signals, and that generates a plurality of clock signals corresponding to the plurality of sets of delayed oscillator signals by passing a delayed oscillator signal when a set of delayed oscillator signals contains a single delayed oscillator signal, and by performing a logical AND operation on the delayed oscillator signals when the set of delayed oscillator signals contain two or more delayed oscillator signals;
- a plurality of drivers that generate a plurality of clock driver output signals in response to the plurality of clock signals, each driver receiving one clock signal and generating one clock driver output signal in response to said one clock signal;
- and
- a comparator that generates the error signal by comparing one of the plurality of clock driver signals and a reference signal.
2 more elements
A circuit for generating a high-resolution periodic waveform, the circuit comprising:
- an oscillator that generates a plurality of delayed oscillator signals in response to an error signal;
- a logic array that receives the delayed oscillator signals, that forms a plurality of sets of delayed oscillator signals, that generates a plurality of intermediate clock signals corresponding to the plurality of sets of delayed oscillator signals by passing a delayed oscillator signal when a set of delayed oscillator signals contains a single delayed oscillator signal, and by performing a logical AND operation on the delayed oscillator signals when the set of delayed oscillator signals contain two or more delayed oscillator signals, that forms a plurality of sets of intermediate clock signals, that generates a plurality of output clock signals corresponding to the plurality of sets of intermediate clock signals by passing an intermediate clock signal when a set of intermediate clock signals contains a single intermediate clock signal, and by performing a logical OR operation on the intermediate clock signals when the set of intermediate clock signals contain two or more intermediate clock signals;
- a plurality of drivers that generate a plurality of clock driver output signals in response to the plurality of output clock signals, each driver receiving one output clock signal and generating one clock driver output signal in response to said one output clock signal;
- and
- a comparator that generates the error signal by comparing one of the plurality of clock driver signals and a reference signal.
2 more elements
A circuit for generating a high-resolution periodic waveform, the circuit comprising:
- an oscillator that generates a plurality of delayed oscillator signals in response to an error signal;
- a logic array that receives the delayed oscillator signals, that forms a plurality of sets of delayed oscillator signals, and that generates a plurality of clock signals corresponding to the plurality of sets of delayed oscillator signals by passing a delayed oscillator signal when a set of delayed oscillator signals contains a single delayed oscillator signal, and by performing a logical AND operation on the delayed oscillator signals when the set of delayed oscillator signals contain two or more delayed oscillator signals;
- and
- a comparator that generates the error signal by comparing one of the plurality of clock signals and a reference signal.
1 more element
Dependencies are inferred from the claim text.