Apparatus and method for synthesis of signals with programmable periods

A digital synthesizer for synthesizing an output signal having one or more user programmable periods comprising:

• a system clock for providing a clock signal;
• an N bit magnitude comparator circuit having first and second compare inputs, each for receiving an N bit digital word, where N is any integer, said magnitude comparator circuit for comparing the magnitudes of said N bit digital words appearing at said first and second compare inputs, and having an output at which a strobe signal transitions to an active state when the magnitudes of said N bit digital words appearing at said first and second compare inputs are equal, said strobe signal comprising said synthesized output signal from said digital synthesizer;
• an accumulator circuit having a data input and a data output, the present value of said accumulator appearing at said data output, said accumulator circuit also having a strobe input coupled to receive said strobe signal from said magnitude comparator circuit, and having a clock input for receiving clock signals from said system clock, both said data input and said data output of said accumulator being M+N bits wide, wherein M and N are integers of any selected value, and N represents the N most significant bits presented at either said data input or said data output of said accumulator, and M represents the M least significant bits, said data input of said accumulator circuit serving to receive a digital input word, U, said accumulator for adding said digital input word, U, to the present value of said accumulator upon receipt of the next clock signal after said strobe signal from said magnitude comparator circuit transitions to said active state, with the resulting sum being presented at said data output of said accumulator, only said N most significant bits appearing at said data output of said accumulator being coupled to said first compare input of said magnitude comparator circuit, and wherein said M least significant bits at said data output are unconnected but effect the value of said N most significant bits through internal carry operations occurring within said accumulator;
• an N bit synchronous counter having a clock input coupled to receive clock signals from said system clock, and having an N bit wide data output coupled to said second compare input of said magnitude comparator circuit, said synchronous counter for incrementing a count upon receipt of each clock signal and presenting said count as an N bit digital word at said second compare input;
• an input coupled to said data input of said accumulator for receiving said digital input word, U, comprised of N most significant bits and M least significant bits.

A digital synthesizer for synthesizing a signal having a user programmable period, comprising:

• a system clock for providing a clock signal having a period equal to T.sub.clock ;
• an N bit magnitude comparator circuit having first and second compare inputs for receiving digital values to be compared, each of said digital values being N bits wide, where N is any integer, and having an output at which a strobe signal becomes active when the digital values at said first and second compare inputs are equal;
• an accumulator circuit having an input and an output, each of which is N+M bits wide, where N and M are each any selected integer, said accumulator having a clock input coupled to receive clock signals from said system clock, said data input of said accumulator circuit for receiving a digital word to be added to the current value presented by said accumulator at said data output thereof, and wherein the most significant N bits of said accumulator output are coupled as a target word to said first compare input of said N bit magnitude comparator circuit, and also having a strobe input coupled to said output of said magnitude comparator circuit for receiving said strobe signal, activation of said strobe signal causing said accumulator circuit to add whatever data word exists at said data input to the value presented as said target word at said accumulator data output upon receiving the next clock signal;
• an N bit synchronous counter circuit having an output at which the count thereof appears, said output coupled to said second compare input of said magnitude comparator circuit, said counter circuit also having a clock input coupled to said system clock such that the value of the count presented at said output is incremented upon receiving each clock signal from said system clock;
• a digitally programmable delay line having a signal input and a signal output and having a clock input coupled to said system clock and having a Q bit data input, for receiving a Q bit digital data input word defining the desired amount of delay, where Q is an integer less than or equal to M, said signal input coupled to receive said strobe signal from said magnitude compare circuit, said Q bit data input of said delay line being coupled to the most significant Q bits of the least significant M bits of said N+M bit data output of said accumulator circuit, said signal output of said digitally programmable delay line presenting the timing corrected digital synthesizer output waveform, said digitally programmable delay line having the property that the propagation delay experienced by a signal propagating from said signal input to said signal output is a linear function of the magnitude of the Q bit digital data input word at said data input of said delay line, said linear function expressed as c+W.times.R=t, where C is a constant fixed delay, W is the magnitude of the Q bit digital data input word appearing at said data input of said delay line, and R is the resolution of said delay line expressed as a unit of time and is equal to 2.sup.-Q .times.T.sub.clock, and where t is the magnitude of the delay imposed by the delay line, and wherein said delay line is adjusted such that the maximum delay imposed by said delay line for the maximum magnitude of W=W.sub. max minus the minimum delay imposed by said delay line for the minimum magnitude of W=0 is equal to the system clock interval T.sub.clock minus the resolution R of said delay line, and
• an input for receiving a digital input word, U, which is N+M bits wide and which defines the desired period of the synthesized signal, said input coupled to said data input of said accumulator circuit.

A digital synthesizer for synthesizing a signal having a user programmable period, comprising:

• a system clock for providing a clock signal having a period equal to T.sub.clock ;
• an N bit magnitude, comparator circuit having first and second compare inputs for receiving digital values to be compared, each of said digital values being N bits wide, where N is any integer, and having an output at which a strobe signal becomes active when the digital values at said first and second compare inputs are equal;
• an accumulator circuit having an input and an output, each of which is N+M bits wide, where N and M are each any selected integer, said accumulator having a clock input coupled to receive clock signals from said system clock, said data input of said accumulator circuit for receiving a digital word to be added to the current value presented by said accumulator at said data output thereof, and wherein the most significant N bits of said accumulator output are coupled as a target Word to said first compare input of said N bit magnitude comparator circuit, and also having a strobe input coupled to said output of said magnitude comparator circuit for receiving said strobe signal activation of said strobe signal causing said accumulator circuit to add whatever data word exists at said data input to the value presented as said target word at said accumulator data output upon receiving the next clock signal;
• an N bit synchronous counter circuit having an output at which the count thereof appears, said output coupled to said second compare input of said magnitude comparator circuit, said counter circuit also having a clock input coupled to said system clock such that the value of the count presented at said output is incremented upon receiving each clock signal from said system clock;
• delay means coupled to said output of said comparator and having an input for receiving a signal defining a desired delay, for adjusting the period of the output signal of said digital synthesizer such that any instantaneous period within the resolution of said delay means can be achieved regardless of the period of said clock signal;
• an input for receiving a digital input word, U, which is N+M bits wide and which defines the desired period of the synthesized signal, said input coupled to said data input of said accumulator circuit.