US 5,394,103 A · Field programmable gate array

Abstract

A FPGA matching the organization and performance of mask programmable gate arrays is presented. The core array is organized into rows of continuous series transistors (CSTs) and rows of small latch/logic blocks. The source/drains and gate of each of the transistors are connected to line segments. The input and output terminals of the blocks are also connected to line segments. Programmable antifuses are located at the intersections of the line segments, which also include others for power and routing purposes. The FPGA can be efficiently configured into a user's application with the flexibility of the CSTs and the efficiency of the latch/logic blocks, which may also be configured into RAM arrays.

Claims86

Dependent claims

A field programmable gate array integrated circuit in a semiconductor substrate, comprising

a plurality of conducting line segments, said conducting line segments intersecting each other and having antifuses at said intersections, said conducting line segments connectable to each other at said intersections by the programming of antifuses connected therebetween;
an array of MOS transistors, each transistor having first and second source/drain region in said substrate and a gate separating said first and second source/drain regions, each of said first and second source/drain regions and each of said gates connected to one of said line segments, said transistors connected in series with a first source/drain region of one transistor merging into a second source/drain region of another transistor;
and
an array of circuit blocks, said array having a plurality of conducting lines in a first direction and a plurality of conducting lines in a second direction, each of said conducting lines connected to each circuit block in said array, each of said circuit blocks further connected to said conducting line segments, the operations of each of said circuit blocks defined into logic and latch functions by selectively interconnecting said conducting line segments through programmed antifuses;
whereby said MOS transistors and said circuit blocks are configurable into a desired circuit by programming selected antifuses.

2 more elements

In an integrated circuit having at least first and second MOS transistors and conducting line segments, each of said MOS transistors including first and second source/drain regions and a gate electrode and being of the same polarity type as the other, said conducting line segments including a first line segment connected to a first source/drain region of said first MOS transistor, a second line segment connected to a first source/drain region of said second MOS transistor and line segments connected to said second source/drain regions and said gate electrodes of said MOS transistors, said first line segment intersecting said second line segment, said first and second line segments having an antifuse connected therebetween, a method of programming said antifuse comprising

setting said first line segment to a first programming voltage;
setting said second line segment and said line segment connected to said gate electrode of said second MOS transistor to a second programming voltage;
and
setting said line segments connected to said second source/drain regions and said gate electrode of said first MOS transistor to a voltage intermediate said first and second programming voltages;
whereby said first line segment is connected to said second line segment.

2 more elements

In an integrated circuit having first and second MOS transistors and conducting line segments, each MOS transistors including first and second source/drain regions and a gate electrode, said first MOS transistor being of one polarity type, said second MOS transistors being of the opposite polarity type, said conducting line segments including a first line segment connected to a first source/drain region of said first MOS transistor, a second line segment connected to a first source/drain region of said second MOS transistor and line segments connected to each of said second source/drain regions and said gate electrodes of each of said MOS transistors, said first line segment intersecting said second line segment, said first and second line segments having an antifuse connected therebetween, a method of programming said antifuse comprising

setting said first line segment to a first programming voltage;
setting said second line segment to a second programming voltage, the polarity of said first programming voltage with respect to said second programming voltage dependent upon said polarity type of said first MOS transistor with respect to said second MOS transistor;
and
setting said line segments connected to each of said second source/drain regions and said gate electrode of said first and second MOS transistors to a voltage intermediate said first and second programming voltages;
whereby said first line segment is connected to said second line segment.

2 more elements

In an integrated circuit having at least first, second, and third MOS transistors and conducting line segments, each of said MOS transistors including first and second source/drain regions and a gate electrode, said first and third MOS transistors being of the one polarity type and said second MOS transistor being of the opposite polarity type, said conducting line segments including a first line segment connected to said first source/drain region of said first MOS transistor, a second line segment connected to said first source/drain regions of said second and third MOS transistors, and line segments connected to each of said second source/drain regions and said gate electrodes of each of said MOS transistors, said first line segment intersecting said second line segment, said first and second line segments having an antifuse connected therebetween, a method of programming said antifuse comprising

setting said first line segment to a first programming voltage;
setting said second line segment and a line segment connected to said gate electrode of said third MOS transistor to a second programming voltage;
and
setting said line segments connected to each of said second source/drain regions of said first, second and third MOS transistors and said gate electrodes of said first and second MOS transistors to a voltage intermediate said first and second programming voltages;
whereby said first line segment is connected to said second line segment.

2 more elements

In an integrated circuit having at least two MOS transistors and conducting line segments, each of said MOS transistors including first and second source/drain regions and a gate electrode, said conducting line segments including a first line segment connected to a first source/drain region of said first MOS transistor, a second line segment connected to a gate electrode of said second MOS transistor, and line segments connected to a second source/drain region and said gate electrode of said first MOS transistor and to first and second source/drain regions of said second MOS transistor, said first line segment intersecting said second line segment, said first line segment and said second line segment having an antifuse connected therebetween, a method of programming said antifuse comprising

setting said first line segment to a first programming voltage;
setting said second line segment to a second programming voltage;
setting said line segments connected to a first source/drain region of said first MOS transistor and to said second source/drains region of said first and second MOS transistors to a voltage intermediate said first and second programming voltages;
and
setting said line segment connected to said gate electrode of said first MOS transistor to such a voltage with respect to said first programming voltage on said first line segment that said first MOS transistor remains off;
whereby said first line segment is connected to said second line segment.

3 more elements

In an integrated circuit having first and second MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode and being of the same polarity type, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions of said MOS transistors, comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said second MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment to said second programming voltage;
and
setting said line segments connected to said second source/drain region of said first MOS transistor and connected to said second source/drain region and gate electrode of said second MOS transistor to said intermediate voltage;
and
setting said line segment connected to said gate electrode of said first MOS transistor to a voltage such that said first MOS transistor does not turn on to connect said first line segment to said line segment connected to said first source/drain region of said second MOS transistor;
whereby line segments connected to said first source/drain regions of said first and second MOS transistors are connected to said first line segment.

7 more elements

In an integrated circuit having first and second MOS transistors and conducting line segments, each MOS transistor including a gate electrode, a first source/drain region and a second source/drain region common to both MOS transistors, said conducting line segments including a first line segment and line segments connected to each gate electrode, said first source/drain regions and said common second source/drain region of said first and second MOS transistors, said first line segment intersecting each of said line segments, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to said first source/drain regions of said MOS transistors comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors and said line segment connected to said first source/drain region of said second MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment and a line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
and
setting said line segments connected to said second common source/drain region and connected to said gate electrode of said first MOS transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
whereby line segments connected to said first source/drain regions of said first and second MOS transistors are connected to said first line segment.

5 more elements

In an integrated circuit having first and second MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode and being of the opposite polarity type, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said second MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said second programming voltage;
setting said first line segment to said first programming voltage;
and
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and connected to said second source/drain region and gate electrode of said second MOS transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
whereby line segments connected to said first source/drain regions of said first and second MOS transistors are connected to said first line segment.

5 more elements

In an integrated circuit having first, second and third MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode, said first and second MOS transistors being of one polarity type and said third MOS transistor being of the opposite polarity type, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions of said first, second and third MOS transistors, comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said second and third MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segments connected to said first source/drain region of said second MOS transistor and to said first programming voltage;
setting said first line segment and said line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
setting said line segments connected to said second source/drain region of said first MOS transistor and connected to said second source/drain region and gate electrode of said second MOS transistor and connected to said first and second source/drain regions and gate electrode of said third transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
then setting said line segment connected to said first source/drain region of said third MOS transistor to said second programming voltage;
setting said first line segment to said first programming voltage;
and
setting said line segments connected to said second source/drain regions and gate electrodes of said first, second and third MOS transistors to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said third MOS transistor;
whereby line segments connected to said first source/drain regions of said first, second and third MOS transistors are connected to said first line segment.

8 more elements

In an integrated circuit having first, second and third MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode, said first and second MOS transistors having a common second source/drain region, said third MOS transistors being of the opposite polarity type from said first and second MOS transistors, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to said first programming voltage;
setting said first line segment to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors and connected to said first source/drain region of said second MOS transistor and connected to said first and second source/drain regions and gate electrode of said third MOS transistors to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment and said line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
setting said line segment connected to said common second source/drain region of said first and second MOS transistors and said line segment connected to said gate electrode of said second MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said third MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
then setting said first line segment to said first programming voltage;
setting said line segment connected to said first source/drain region of said third MOS transistor to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors and line segments connected to said second source/drain region and gate electrode of said third transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said third MOS transistor;
whereby line segments connected to said first source/drain regions of said first, second and third MOS transistors are connected to said first line segment.

7 more elements

In an integrated circuit having first, second, third and fourth MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode, said first and second MOS transistors having a common second source/drain region, said third and fourth MOS transistors being of the opposite polarity type from said first and second MOS transistors and having a common second source/drain region, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions of said first, second, third and fourth MOS transistors, comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to said first programming voltage;
setting said first line segment to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors, said line segment connected to said first source/drain region of said second MOS transistor, and line segments connected to said first and second source/drain regions and gate electrode of said third and fourth MOS transistors to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment and said line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
setting said line segment connected to said common second source/drain region of said first and second MOS transistors, said line segment connected to said gate electrode of said second MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said third and fourth MOS transistors to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
then setting said first line segment to said first programming voltage;
setting said line segment connected to said first source/drain region of said third MOS transistor to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors, said line segments connected to said common second source/drain region and gate electrodes of said third and fourth transistors and said line segment connected to first source/drain region of said fourth MOS transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said third MOS transistor;
then setting said first line segment and said line segment connected to said gate electrode of said third MOS transistor to said first programming voltage;
setting said line segment connected to said first source/drain region of said fourth MOS transistor to said second programming voltage;
and
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors, said line segments connected to said common second source/drain region and gate electrode of said fourth transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said fourth MOS transistor;
whereby line segments connected to said first source/drain regions of said first, second, third and fourth MOS transistors are connected to said first line segment.

11 more elements

In an integrated circuit having a plurality of NMOS and PMOS transistors and conducting line segments, each NMOS and PMOS transistor including first and second source/drain regions and a gate electrode, said conducting line segments including line segments connected to said source/drain regions and gate electrodes of said NMOS and PMOS transistors and unconnected line segments, said line segments crossing each other in a predetermined pattern at intersections, said intersections having antifuses connected between said crossing line segments, a method of connecting a first source/drain region or a gate electrode of preselected NMOS and PMOS transistors, comprising

connecting all line segments connected to first source/drain regions of said preselected NMOS transistors and an arbitrary number of line segments connected to gate electrodes of said preselected NMOS and PMOS transistors to a first line segment;
connecting all line segments connected to first source/drain regions of said preselected PMOS transistors and the remainder of line segments connected to gate electrodes of said preselected NMOS and PMOS transistors to a second line segment;
setting said first line segment to a first programming voltage;
setting said second line segment to a second programming voltage;
setting said line segments connected to second source/drain regions of said preselected NMOS and PMOS transistors and said line segments connected to a voltage intermediate said first and second programming voltages;
whereby said first source/drain regions and said gate electrodes of said preselected NMOS and PMOS transistors are connected.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application

08/201,448Filed 24 Feb 1994 · division

Priority

18 Mar 1991

Granted

28 Feb 1995

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H03K 19/1776
Structural details of configuration resources: for memories
H03K 19/177
Using elementary logic circuits as components: arranged in matrix form
H03K 19/17704
Arranged in matrix form: the logic functions being realised by the interconnection of rows and columns
H03K 19/17736
Arranged in matrix form: structural details of routing resources

Abstract

Claims86

Dependent claims

A field programmable gate array integrated circuit in a semiconductor substrate, comprising

a plurality of conducting line segments, said conducting line segments intersecting each other and having antifuses at said intersections, said conducting line segments connectable to each other at said intersections by the programming of antifuses connected therebetween;
an array of MOS transistors, each transistor having first and second source/drain region in said substrate and a gate separating said first and second source/drain regions, each of said first and second source/drain regions and each of said gates connected to one of said line segments, said transistors connected in series with a first source/drain region of one transistor merging into a second source/drain region of another transistor;
and
an array of circuit blocks, said array having a plurality of conducting lines in a first direction and a plurality of conducting lines in a second direction, each of said conducting lines connected to each circuit block in said array, each of said circuit blocks further connected to said conducting line segments, the operations of each of said circuit blocks defined into logic and latch functions by selectively interconnecting said conducting line segments through programmed antifuses;
whereby said MOS transistors and said circuit blocks are configurable into a desired circuit by programming selected antifuses.

2 more elements

setting said first line segment to a first programming voltage;
setting said second line segment and said line segment connected to said gate electrode of said second MOS transistor to a second programming voltage;
and
setting said line segments connected to said second source/drain regions and said gate electrode of said first MOS transistor to a voltage intermediate said first and second programming voltages;
whereby said first line segment is connected to said second line segment.

2 more elements

setting said first line segment to a first programming voltage;
setting said second line segment to a second programming voltage, the polarity of said first programming voltage with respect to said second programming voltage dependent upon said polarity type of said first MOS transistor with respect to said second MOS transistor;
and
setting said line segments connected to each of said second source/drain regions and said gate electrode of said first and second MOS transistors to a voltage intermediate said first and second programming voltages;
whereby said first line segment is connected to said second line segment.

2 more elements

setting said first line segment to a first programming voltage;
setting said second line segment and a line segment connected to said gate electrode of said third MOS transistor to a second programming voltage;
and
setting said line segments connected to each of said second source/drain regions of said first, second and third MOS transistors and said gate electrodes of said first and second MOS transistors to a voltage intermediate said first and second programming voltages;
whereby said first line segment is connected to said second line segment.

2 more elements

setting said first line segment to a first programming voltage;
setting said second line segment to a second programming voltage;
setting said line segments connected to a first source/drain region of said first MOS transistor and to said second source/drains region of said first and second MOS transistors to a voltage intermediate said first and second programming voltages;
and
setting said line segment connected to said gate electrode of said first MOS transistor to such a voltage with respect to said first programming voltage on said first line segment that said first MOS transistor remains off;
whereby said first line segment is connected to said second line segment.

3 more elements

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said second MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment to said second programming voltage;
and
setting said line segments connected to said second source/drain region of said first MOS transistor and connected to said second source/drain region and gate electrode of said second MOS transistor to said intermediate voltage;
and
setting said line segment connected to said gate electrode of said first MOS transistor to a voltage such that said first MOS transistor does not turn on to connect said first line segment to said line segment connected to said first source/drain region of said second MOS transistor;
whereby line segments connected to said first source/drain regions of said first and second MOS transistors are connected to said first line segment.

7 more elements

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors and said line segment connected to said first source/drain region of said second MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment and a line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
and
setting said line segments connected to said second common source/drain region and connected to said gate electrode of said first MOS transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
whereby line segments connected to said first source/drain regions of said first and second MOS transistors are connected to said first line segment.

5 more elements

In an integrated circuit having first and second MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode and being of the opposite polarity type, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said second MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said second programming voltage;
setting said first line segment to said first programming voltage;
and
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and connected to said second source/drain region and gate electrode of said second MOS transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
whereby line segments connected to said first source/drain regions of said first and second MOS transistors are connected to said first line segment.

5 more elements

setting said line segment connected to said first source/drain region of said first MOS transistor to a first programming voltage;
setting said first line segment to a second programming voltage;
setting said line segments connected to said second source/drain region and gate electrode of said first MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said second and third MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segments connected to said first source/drain region of said second MOS transistor and to said first programming voltage;
setting said first line segment and said line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
setting said line segments connected to said second source/drain region of said first MOS transistor and connected to said second source/drain region and gate electrode of said second MOS transistor and connected to said first and second source/drain regions and gate electrode of said third transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
then setting said line segment connected to said first source/drain region of said third MOS transistor to said second programming voltage;
setting said first line segment to said first programming voltage;
and
setting said line segments connected to said second source/drain regions and gate electrodes of said first, second and third MOS transistors to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said third MOS transistor;
whereby line segments connected to said first source/drain regions of said first, second and third MOS transistors are connected to said first line segment.

8 more elements

In an integrated circuit having first, second and third MOS transistors and conducting line segments, each MOS transistor including first and second source/drain regions and a gate electrode, said first and second MOS transistors having a common second source/drain region, said third MOS transistors being of the opposite polarity type from said first and second MOS transistors, said conducting line segments including a first line segment and line segments connected to each of said first and second source/drain regions and gate electrodes of each of said MOS transistors, said first line segment intersecting each of said line segments connected to said first and second source/drain regions and gate electrodes of said MOS transistors, said first line segment and each of said line segments having an antifuse connected therebetween, a method of programming antifuses between said first line segment and line segments connected to first source/drain regions comprising

setting said line segment connected to said first source/drain region of said first MOS transistor to said first programming voltage;
setting said first line segment to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors and connected to said first source/drain region of said second MOS transistor and connected to said first and second source/drain regions and gate electrode of said third MOS transistors to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment and said line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
setting said line segment connected to said common second source/drain region of said first and second MOS transistors and said line segment connected to said gate electrode of said second MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said third MOS transistor to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
then setting said first line segment to said first programming voltage;
setting said line segment connected to said first source/drain region of said third MOS transistor to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors and line segments connected to said second source/drain region and gate electrode of said third transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said third MOS transistor;
whereby line segments connected to said first source/drain regions of said first, second and third MOS transistors are connected to said first line segment.

7 more elements

setting said line segment connected to said first source/drain region of said first MOS transistor to said first programming voltage;
setting said first line segment to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors, said line segment connected to said first source/drain region of said second MOS transistor, and line segments connected to said first and second source/drain regions and gate electrode of said third and fourth MOS transistors to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said first MOS transistor;
then setting said line segment connected to said first source/drain region of said second MOS transistor to said first programming voltage;
setting said first line segment and said line segment connected to said gate electrode of said first MOS transistor to said second programming voltage;
setting said line segment connected to said common second source/drain region of said first and second MOS transistors, said line segment connected to said gate electrode of said second MOS transistor and line segments connected to said first and second source/drain regions and gate electrode of said third and fourth MOS transistors to a voltage intermediate said first and second programming voltages so that said first line segment is connected to said line segment connected to said first source/drain region of said second MOS transistor;
then setting said first line segment to said first programming voltage;
setting said line segment connected to said first source/drain region of said third MOS transistor to said second programming voltage;
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors, said line segments connected to said common second source/drain region and gate electrodes of said third and fourth transistors and said line segment connected to first source/drain region of said fourth MOS transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said third MOS transistor;
then setting said first line segment and said line segment connected to said gate electrode of said third MOS transistor to said first programming voltage;
setting said line segment connected to said first source/drain region of said fourth MOS transistor to said second programming voltage;
and
setting said line segments connected to said common second source/drain region and gate electrodes of said first and second MOS transistors, said line segments connected to said common second source/drain region and gate electrode of said fourth transistor to said intermediate voltage so that said first line segment is connected to said line segment connected to said first source/drain region of said fourth MOS transistor;
whereby line segments connected to said first source/drain regions of said first, second, third and fourth MOS transistors are connected to said first line segment.

11 more elements

connecting all line segments connected to first source/drain regions of said preselected NMOS transistors and an arbitrary number of line segments connected to gate electrodes of said preselected NMOS and PMOS transistors to a first line segment;
connecting all line segments connected to first source/drain regions of said preselected PMOS transistors and the remainder of line segments connected to gate electrodes of said preselected NMOS and PMOS transistors to a second line segment;
setting said first line segment to a first programming voltage;
setting said second line segment to a second programming voltage;
setting said line segments connected to second source/drain regions of said preselected NMOS and PMOS transistors and said line segments connected to a voltage intermediate said first and second programming voltages;
whereby said first source/drain regions and said gate electrodes of said preselected NMOS and PMOS transistors are connected.

3 more elements

Dependencies are inferred from the claim text.

Field programmable gate array

Life of this patent

Abstract

Claims86

Field programmable gate array

Life of this patent

Abstract

Claims86