Output circuit comprising bipolar transistors for driving CMOS circuit to reduce power consumption of the output circuit and avoid erroneous operation of the CMOS circuit

An output circuit having a plurality of bipolar transistors for driving a CMIS circuit, wherein said output circuit comprises:

• a high-potential power supply line;
• a low-potential power supply line;
• an output terminal for outputting a signal to said CMIS circuit;
• output transistors connected in series, at a series connection node common to said output terminal, between said high-potential power supply line and said low-potential power supply line;
• an output level maintaining transistor connected between said output terminal of said output circuit and said low-potential power supply line, said output level maintaining transistor maintaining a level of said output terminal at a specific high potential by transmitting a current from said output terminal to said low-potential power supply line while said output circuit is outputting a high level signal to said output terminal, said output level maintaining transistor being cur OFF while said output circuit is outputting a low level signal to said output terminal;
• a current control transistor connected to said output level maintaining transistor in a Current-Mirror connection and controlling the current flowing through said output level maintaining transistor;
• and
• a switching control transistor which is connected in series between said high-potential power supply line and said low-potential power supply line through a constant current source and which controls the current control transistor.

An output circuit having a plurality of bipolar transistors for driving a CMIS circuit, wherein said output circuit comprises:

• a high-potential power supply line;
• a low-potential power supply line;
• an output terminal for outputting a signal to said CMIS circuit;
• output transistors connected in series, at a series connection node common to said output terminal, between said high-potential power supply line and said low-potential power supply line, said output transistors comprising a first Darlington connection of a first pair of bipolar transistors connected to said high-potential power supply line for outputting the high level signal to said output terminal, and a second Darlington connection of a second pair of bipolar transistors connected to said low-potential power supply line for outputting the low level signal to said output terminal;
• and
• an output level maintaining transistor connected between said output terminal of said output circuit and said low-potential power supply line, said output level maintaining transistor maintaining a level of said output terminal at a specific high potential by transmitting a current from said output terminal to said low-potential power supply line while said output circuit is outputting a high level signal to said output terminal, and said output level maintaining transistor being cut OFF while said output circuit is outputting a low level signal to said output terminal.

An output circuit having a plurality of bipolar transistors for driving a CMIS circuit, a high-potential power supply of said output circuit being of a higher potential than that of a high-potential power supply of said CMIS circuit, said output circuit comprising:

• a high-potential power supply line;
• a low-potential power supply line;
• an output terminal for outputting a signal to said CMIS circuit;
• output transistors connected in series, at a series connection node common to said output terminal, between said high-potential power supply line and said low-potential power supply line;
• and
• an output level maintaining transistor connected between said output terminal of said output circuit and said low-potential power supply line, said output level maintaining transistor maintaining said output terminal at a specific high potential by transmitting a current from said output terminal to said low-potential power supply line while said output circuit is outputting a high level signal to said output terminal, and said output level maintaining transistor being cut OFF while said output circuit is outputting a low level signal to said output terminal.